MC9S12NE64CPV Freescale Semiconductor, MC9S12NE64CPV Datasheet - Page 334

• Manufacturer Part Number: MC9S12NE64CPV
• Description: IC MCU 25MHZ ETHERNT/PHY 112LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12NE64CPV

• Mfg Application Notes: MC9S12NE64 Integrated Ethernet Controller Implementing an Ethernet Interface with the MC9S12NE64 Web Server Development with MC9S12NE64 and Open TCP
• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.375 V ~ 3.465 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• Data Bus Width: 16 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, SCI, SPI
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 16 bit
• Operating Supply Voltage: - 0.3 V to + 3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 65 C
• On-chip Adc: 10 bit
• For Use With: EVB9S12NE64E - BOARD EVAL FOR 9S12NE64DEMO9S12NE64E - DEMO BOARD FOR 9S12NE64
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No RoHS Version Available

Chapter 11 Ethernet Media Access Controller (EMACV1)
If a receive frame length is less than 64 bytes, the receive frame is considered a fragment and is dropped.
Most fragments are the result of a collision, and as such are a completely normal and expected event on an
Ethernet.
If a receive frame length exceeds 1518, the receive frame is considered too long and is an error. The RXEIF
bit becomes set and if not masked (RXEIE set to 1), the EMAC generates the receive error interrupt.
If MII_RXER is asserted during reception, indicating a media error, the RXEIF bit becomes set and if not
masked (RXEIE set to 1), the EMAC generates the receive error interrupt.
If the type/length field is less-than or equal-to 1500 (but greater than 46), a length mismatch error occurs
if the receive frame data field length does not match the length specified in the type/length field. If the
type/length field is less than or equal to 46, a length mismatch error occurs if the receive frame data field
length is not 46. If a length mismatch error occurs, the RXEIF bit becomes set and if not masked (RXEIE
set to 1), the EMAC generates the receive error interrupt.
The EMAC receiver automatically calculates a 4-byte frame check sequence from the receive frame and
compares it with the CRC data suffixed to the receive frame. If a CRC error occurs, the RXEIF bit becomes
set and if not masked (RXEIE set to 1), the EMAC generates the receive error interrupt.
After the end of frame delimiter, the received frame is truncated to the nearest byte boundary. If there is an
extra nibble, this dribble nibble is discarded. If the CRC value in the received frame is correct, the frame
is accepted as valid. If the CRC value is incorrect and there is a dribble nibble, an alignment error has
occurred and the RXEIF bit becomes set and if not masked (RXEIE set to 1), the EMAC generates the
receive error interrupt.
Frames that exceed the MAXFL field in byte length are not truncated. However, the BREIF bit becomes
set and if not masked (BREIE set to 1), the EMAC generates the babbling receive error interrupt.
If a receive frame exceeds the receive buffer size, the corresponding receive overrun error flag is set. In the
overrun error event, the frame is not accepted and neither the corresponding complete flag nor the receive
error flag is set. A babbling receive error condition is ignored if it occurs after a buffer overrun event and
thus BREIF does not become set.
Upon MAC flow control PAUSE frame reception, the RFCIF bit in the IEVENT register is asserted. If not
masked (RFCIE is set), a receive flow control interrupt is pending while this flag is set. PAUSE frames may
be accepted even if both receive buffers are full. The frame is accepted and the RFCIF flag is set only if
there no receive error.
When frame reception to either receive buffer A or receive buffer B is complete, the corresponding receive
buffer complete flag is set, the value in the corresponding receive end-of-frame pointer is valid. If not
masked (corresponding receive buffer complete interrupt enable is set to 1), the EMAC generates the
corresponding receive buffer complete interrupt. The receiver buffer complete flag is set only if there are
no receive errors and the frame has not been accepted as a MAC flow control PAUSE frame. If both
receiver buffer complete flags are set, new receive frames are dropped until one of the complete flags is
cleared.
The receiver receives back-to-back frames with a minimum spacing of at least 96 bit times. If an interframe
gap between receive frames is less than 96 bit times, the latter frame is not guaranteed to be accepted by
the receiver.
MC9S12NE64 Data Sheet, Rev. 1.1
334
Freescale Semiconductor