MC908JB8FBE Freescale Semiconductor, MC908JB8FBE Datasheet - Page 81

• Manufacturer Part Number: MC908JB8FBE
• Description: IC MCU 8K FLASH 3MHZ 44-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908JB8FBE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 3MHz
• Connectivity: USB
• Peripherals: LVD, POR, PWM
• Number Of I /o: 37
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 44-QFP
• Processor Series: HC08JB
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: USB
• Maximum Clock Frequency: 3 MHz
• Number Of Programmable I/os: 37
• Number Of Timers: 2
• Operating Supply Voltage: 5.25 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, DEMO908GZ60E, M68EML08GZE, KITUSBSPIDGLEVME, KITUSBSPIEVME, KIT33810EKEVME
• Minimum Operating Temperature: 0 C
• Controller Family/series: HC08
• No. Of I/o's: 37
• Ram Memory Size: 256Byte
• Cpu Speed: 8MHz
• No. Of Timers: 1
• Embedded Interface Type: SCI, SPI
• Rohs Compliant: Yes
• Package: 44PQFP
• Family Name: HC08
• Maximum Speed: 3 MHz
• Cpu Family: HC08
• Device Core Size: 8b
• Frequency (max): 3MHz
• Total Internal Ram Size: 256Byte
• # I/os (max): 37
• Number Of Timers - General Purpose: 2
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4V
• Instruction Set Architecture: CISC
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 44
• Package Type: PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3
Freescale Semiconductor
CLR opr
CLRA
CLRX
CLRH
CLR opr,X
CLR ,X
CLR opr,SP
CMP #opr
CMP opr
CMP opr
CMP opr,X
CMP opr,X
CMP ,X
CMP opr,SP
CMP opr,SP
COM opr
COMA
COMX
COM opr,X
COM ,X
COM opr,SP
CPHX #opr
CPHX opr
CPX #opr
CPX opr
CPX opr
CPX ,X
CPX opr,X
CPX opr,X
CPX opr,SP
CPX opr,SP
DAA
DBNZ opr,rel
DBNZA rel
DBNZX rel
DBNZ opr,X,rel
DBNZ X,rel
DBNZ opr,SP,rel
DEC opr
DECA
DECX
DEC opr,X
DEC ,X
DEC opr,SP
DIV
Source
Form
Clear
Compare A with M
Complement (One’s Complement)
Compare H:X with M
Compare X with M
Decimal Adjust A
Decrement and Branch if Not Zero
Decrement
Divide
Operation
Table 6-1. Instruction Set Summary (Sheet 4 of 9)
Central Processor Unit (CPU)
A ← (A) – 1 or M ← (M) – 1 or X ← (X) – 1
PC ← (PC) + 3 + rel ? (result) ≠ 0
PC ← (PC) + 2 + rel ? (result) ≠ 0
PC ← (PC) + 2 + rel ? (result) ≠ 0
PC ← (PC) + 3 + rel ? (result) ≠ 0
PC ← (PC) + 2 + rel ? (result) ≠ 0
PC ← (PC) + 4 + rel ? (result) ≠ 0
M ← (M) = $FF – (M)
M ← (M) = $FF – (M)
M ← (M) = $FF – (M)
M ← (M) = $FF – (M)
A ← (A) = $FF – (M)
X ← (X) = $FF – (M)
(H:X) – (M:M + 1)
H ← Remainder
A ← (H:A)/(X)
Description
M ← (M) – 1
M ← (M) – 1
M ← (M) – 1
M ← (M) – 1
A ← (A) – 1
X ← (X) – 1
M ← $00
M ← $00
M ← $00
M ← $00
A ← $00
X ← $00
H ← $00
(A) – (M)
(X) – (M)
(A)
10
U – –
V H I N Z C
0 – – 0 1 –
0 – –
– – – – – –
– – – –
– –
– –
– –
– –
Effect on
CCR
Central Processor Unit (CPU)
1
–
Instruction Set Summary
DIR
INH
INH
INH
IX1
IX
SP1
IMM
DIR
EXT
IX2
IX1
IX
SP1
SP2
DIR
INH
INH
IX1
IX
SP1
IMM
DIR
IMM
DIR
EXT
IX2
IX1
IX
SP1
SP2
INH
DIR
INH
INH
IX1
IX
SP1
DIR
INH
INH
IX1
IX
SP1
INH
Technical Data
9E6F
9EE1
9ED1
9EE3
9ED3
9E6B
9E6A
9E63
8C
C1
D1
C3
D3
3F
4F
5F
6F
7F
A1
B1
E1
F1
33
43
53
63
73
65
75
A3
B3
E3
F3
72
3B
4B
5B
6B
7B
3A
4A
5A
6A
7A
52
dd
ff
ff
ii
dd
hh ll
ee ff
ff
ff
ee ff
dd
ff
ff
ii ii+1
dd
ii
dd
hh ll
ee ff
ff
ff
ee ff
dd rr
rr
rr
ff rr
rr
ff rr
dd
ff
ff
81
3
1
1
1
3
2
4
2
3
4
4
3
2
4
5
4
1
1
4
3
5
3
4
2
3
4
4
3
2
4
5
2
5
3
3
5
4
6
4
1
1
4
3
5
7