MC908JB8FBE Freescale Semiconductor, MC908JB8FBE Datasheet - Page 80

• Manufacturer Part Number: MC908JB8FBE
• Description: IC MCU 8K FLASH 3MHZ 44-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908JB8FBE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 3MHz
• Connectivity: USB
• Peripherals: LVD, POR, PWM
• Number Of I /o: 37
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 44-QFP
• Processor Series: HC08JB
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: USB
• Maximum Clock Frequency: 3 MHz
• Number Of Programmable I/os: 37
• Number Of Timers: 2
• Operating Supply Voltage: 5.25 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, DEMO908GZ60E, M68EML08GZE, KITUSBSPIDGLEVME, KITUSBSPIEVME, KIT33810EKEVME
• Minimum Operating Temperature: 0 C
• Controller Family/series: HC08
• No. Of I/o's: 37
• Ram Memory Size: 256Byte
• Cpu Speed: 8MHz
• No. Of Timers: 1
• Embedded Interface Type: SCI, SPI
• Rohs Compliant: Yes
• Package: 44PQFP
• Family Name: HC08
• Maximum Speed: 3 MHz
• Cpu Family: HC08
• Device Core Size: 8b
• Frequency (max): 3MHz
• Total Internal Ram Size: 256Byte
• # I/os (max): 37
• Number Of Timers - General Purpose: 2
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4V
• Instruction Set Architecture: CISC
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 44
• Package Type: PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Central Processor Unit (CPU)
Technical Data
80
BNE rel
BPL rel
BRA rel
BRCLR n,opr,rel Branch if Bit n in M Clear
BRN rel
BRSET n,opr,rel Branch if Bit n in M Set
BSET n,opr
BSR rel
CBEQ opr,rel
CBEQA #opr,rel
CBEQX #opr,rel
CBEQ opr,X+,rel
CBEQ X+,rel
CBEQ opr,SP,rel
CLC
CLI
Source
Form
Branch if Not Equal
Branch if Plus
Branch Always
Branch Never
Set Bit n in M
Branch to Subroutine
Compare and Branch if Equal
Clear Carry Bit
Clear Interrupt Mask
Operation
Table 6-1. Instruction Set Summary (Sheet 3 of 9)
Central Processor Unit (CPU)
PC ← (PC) + 3 + rel ? (A) – (M) = $00
PC ← (PC) + 3 + rel ? (A) – (M) = $00
PC ← (PC) + 3 + rel ? (X) – (M) = $00
PC ← (PC) + 3 + rel ? (A) – (M) = $00
PC ← (PC) + 2 + rel ? (A) – (M) = $00
PC ← (PC) + 4 + rel ? (A) – (M) = $00
PC ← (PC) + 3 + rel ? (Mn) = 0
PC ← (PC) + 3 + rel ? (Mn) = 1
PC ← (PC) + 2 + rel ? (N) = 0
PC ← (PC) + 2 + rel ? (Z) = 0
SP ← (SP) – 1; push (PCH)
PC ← (PC) + 2; push (PCL)
PC ← (PC) + 2 + rel
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3
PC ← (PC) + rel
PC ← (PC) + 2
SP ← (SP) – 1
Description
Mn ← 1
C ← 0
I ← 0
V H I N Z C
– – – – – – REL
– – – – – – REL
– – – – – – REL
– – – – –
– – – – – – REL
– – – – –
– – – – – –
– – – – – – REL
– – – – – –
– – – – – 0 INH
– – 0 – – – INH
Effect on
CCR
Freescale Semiconductor
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
DIR
IMM
IMM
IX1+
IX+
SP1
9E61
AD
2A
0B
0D
0A
0C
0E
1A
1C
1E
9A
26
20
01
03
05
07
09
0F
21
00
02
04
06
08
10
12
14
16
18
31
41
51
61
71
98
rr
rr
rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd
dd
dd
dd
dd
dd
dd
dd
rr
dd rr
ii rr
ii rr
ff rr
rr
ff rr
3
3
3
5
5
5
5
5
5
5
5
3
5
5
5
5
5
5
5
5
4
4
4
4
4
4
4
4
4
5
4
4
5
4
6
1
2