MC908JB8FBE Freescale Semiconductor, MC908JB8FBE Datasheet - Page 243

IC MCU 8K FLASH 3MHZ 44-QFP

MC908JB8FBE

Manufacturer Part Number
MC908JB8FBE
Description
IC MCU 8K FLASH 3MHZ 44-QFP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet

Specifications of MC908JB8FBE

Core Processor
HC08
Core Size
8-Bit
Speed
3MHz
Connectivity
USB
Peripherals
LVD, POR, PWM
Number Of I /o
37
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
44-QFP
Processor Series
HC08JB
Core
HC08
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
USB
Maximum Clock Frequency
3 MHz
Number Of Programmable I/os
37
Number Of Timers
2
Operating Supply Voltage
5.25 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Development Tools By Supplier
FSICEBASE, DEMO908GZ60E, M68EML08GZE, KITUSBSPIDGLEVME, KITUSBSPIEVME, KIT33810EKEVME
Minimum Operating Temperature
0 C
Controller Family/series
HC08
No. Of I/o's
37
Ram Memory Size
256Byte
Cpu Speed
8MHz
No. Of Timers
1
Embedded Interface Type
SCI, SPI
Rohs Compliant
Yes
Package
44PQFP
Family Name
HC08
Maximum Speed
3 MHz
Cpu Family
HC08
Device Core Size
8b
Frequency (max)
3MHz
Total Internal Ram Size
256Byte
# I/os (max)
37
Number Of Timers - General Purpose
2
Operating Supply Voltage (typ)
5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
4V
Instruction Set Architecture
CISC
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
44
Package Type
PQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

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Technical Data — MC68HC908JB8•MC68HC08JB8•MC68HC08JT8
16.1 Contents
16.2 Introduction
16.3 Functional Description
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3
Freescale Semiconductor
16.2
16.3
16.4
16.5
16.5.1
16.5.2
This section describes the low-voltage inhibit module (LVI), which
monitors the voltage on the V
voltage falls to the LVI trip (V
Figure 16-1
after a reset. The LVI module contains a bandgap reference circuit and
comparator. Setting LVI disable bit (LVID) disables the LVI to monitor
V
The LVI module generates one output signal:
LVI Reset — an reset signal will be generated to reset the CPU when
V
DD
DD
voltage.
drops to below the set trip point.
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .243
LVI Control Register (CONFIG) . . . . . . . . . . . . . . . . . . . . . . .244
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .244
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .244
Section 16. Low Voltage Inhibit (LVI)
shows the structure of the LVI module. The LVI is enabled
Low Voltage Inhibit (LVI)
DD
LVR
pin and generates a reset when the V
) voltage.
Technical Data
243
DD

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