MC908JB8FBE Freescale Semiconductor, MC908JB8FBE Datasheet - Page 205

IC MCU 8K FLASH 3MHZ 44-QFP

MC908JB8FBE

Manufacturer Part Number
MC908JB8FBE
Description
IC MCU 8K FLASH 3MHZ 44-QFP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet

Specifications of MC908JB8FBE

Core Processor
HC08
Core Size
8-Bit
Speed
3MHz
Connectivity
USB
Peripherals
LVD, POR, PWM
Number Of I /o
37
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
44-QFP
Processor Series
HC08JB
Core
HC08
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
USB
Maximum Clock Frequency
3 MHz
Number Of Programmable I/os
37
Number Of Timers
2
Operating Supply Voltage
5.25 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Development Tools By Supplier
FSICEBASE, DEMO908GZ60E, M68EML08GZE, KITUSBSPIDGLEVME, KITUSBSPIEVME, KIT33810EKEVME
Minimum Operating Temperature
0 C
Controller Family/series
HC08
No. Of I/o's
37
Ram Memory Size
256Byte
Cpu Speed
8MHz
No. Of Timers
1
Embedded Interface Type
SCI, SPI
Rohs Compliant
Yes
Package
44PQFP
Family Name
HC08
Maximum Speed
3 MHz
Cpu Family
HC08
Device Core Size
8b
Frequency (max)
3MHz
Total Internal Ram Size
256Byte
# I/os (max)
37
Number Of Timers - General Purpose
2
Operating Supply Voltage (typ)
5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
4V
Instruction Set Architecture
CISC
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
44
Package Type
PQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

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12.4.2 Data Direction Register B
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3
Freescale Semiconductor
NOTE:
NOTE:
Address:
PTB[7:0] — Port B Data Bits
Data direction register B determines whether each port B pin is an input
or an output. Writing a logic 1 to a DDRB bit enables the output buffer for
the corresponding port B pin; a logic 0 disables the output buffer.
DDRB[7:0] — Data Direction Register B Bits
Avoid glitches on port B pins by writing to the port B data register before
changing data direction register B bits from 0 to 1.
For those devices packaged in a 20-pin PDIP, 20-pin SOIC, and 28-pin
SOIC package, PTB7–PTB0 are not connected. DDRB7–DDRB0
should be set to a 1 to configure PTB7–PTB0 as outputs.
Figure 12-7
Reset:
Read:
Write:
These read/write bits are software-programmable. Data direction of
each port B pin is under the control of the corresponding bit in data
direction register B. Reset has no effect on port B data.
The port B pullup enable bit, PBP, in the port option control register
(POCR) enables pullups on port B pins if the respective pin is
configured as an input. (See
These read/write bits control port B data direction. Reset clears
DDRB[7:0], configuring all port B pins as inputs.
1 = Corresponding port B pin configured as output
0 = Corresponding port B pin configured as input
DDRB7
$0005
Bit 7
0
Figure 12-6. Data Direction Register B (DDRB)
shows the port B I/O logic.
Input/Output Ports (I/O)
DDRB6
6
0
DDRB5
0
5
12.8 Port
DDRB4
0
4
DDRB3
Options.)
3
0
DDRB2
2
0
Input/Output Ports (I/O)
DDRB1
1
0
Technical Data
DDRB0
Bit 0
Port B
0
205

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