ADUC7024BSTZ62 Analog Devices Inc, ADUC7024BSTZ62 Datasheet - Page 41

• Manufacturer Part Number: ADUC7024BSTZ62
• Description: IC MCU FLASH 62K ANLG I/O 64LQFP
• Manufacturer: Analog Devices Inc
• Series: MicroConverter® ADuC7xxxr

Specifications of ADUC7024BSTZ62

• Core Size: 16/32-Bit
• Program Memory Size: 62KB (62K x 8)
• Design Resources: Sensing Low-g Acceleration Using ADXL345 Digital Accelerometer Connected to ADuC7024 (CN0133)
• Core Processor: ARM7
• Speed: 44MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: PLA, PWM, PSM, Temp Sensor, WDT
• Number Of I /o: 30
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 10x12b; D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 64-LQFP
• Controller Family/series: (ARM7) ADUC
• No. Of I/o's: 30
• Ram Memory Size: 8KB
• Cpu Speed: 44MHz
• No. Of Timers: 4
• Digital Ic Case Style: LQFP
• Embedded Interface Type: I2C, SPI, UART
• Rohs Compliant: Yes
• Package: 64LQFP
• Device Core: ARM7TDMI
• Family Name: ADuC7xxx
• Maximum Speed: 44 MHz
• Operating Supply Voltage: 3.3 V
• Data Bus Width: 16|32 Bit
• Number Of Programmable I/os: 30
• Interface Type: I2C/SPI/UART
• On-chip Adc: 10-chx12-bit
• On-chip Dac: 2-chx12-bit
• Number Of Timers: 4
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

ADC CIRCUIT OVERVIEW
The analog-to-digital converter (ADC) incorporates a fast,
multichannel, 12-bit ADC. It can operate from 2.7 V to 3.6 V
supplies and is capable of providing a throughput of up to
1 MSPS when the clock source is 41.78 MHz. This block
provides the user with a multichannel multiplexer, a differential
track-and-hold, an on-chip reference, and an ADC.
The ADC consists of a 12-bit successive approximation converter
based around two capacitor DACs. Depending on the input
signal configuration, the ADC can operate in one of three modes.
•
•
•
The converter accepts an analog input range of 0 V to V
operating in single-ended or pseudo differential mode. In fully
differential mode, the input signal must be balanced around a
common-mode voltage (V
maximum amplitude of 2 V
A high precision, low drift, factory calibrated, 2.5 V reference is
provided on-chip. An external reference can also be connected as
described in the Band Gap Reference section.
Single or continuous conversion modes can be initiated in the
software. An external CONV
the on-chip PLA, or a Timer0 or Timer1 overflow can also be
used to generate a repetitive trigger for ADC conversions.
A voltage output from an on-chip band gap reference propor-
tional to absolute temperature can also be routed through the
front-end ADC multiplexer, effectively an additional ADC channel
input. This facilitates an internal temperature sensor channel
that measures die temperature to an accuracy of ±3°C.
TRANSFER FUNCTION
Pseudo Differential and Single-Ended Modes
In pseudo differential or single-ended mode, the input range is
0 V to V
differential and single-ended modes with
Figure 38. Examples of Balanced Signals in Fully Differential Mode
Fully differential mode, for small and balanced signals
Single-ended mode, for any single-ended signals
Pseudo differential mode, for any single-ended signals,
taking advantage of the common-mode rejection offered
by the pseudo differential input
1 LSB = FS/4096, or
2.5 V/4096 = 0.61 mV, or
610 μV when V
REF
AV
. The output coding is straight binary in pseudo
V
CM
DD
0
REF
= 2.5 V
V
CM
CM
REF
) in the 0 V to AV
START
2V
V
(see Figure 38).
CM
REF
pin, an output generated from
2V
REF
DD
2V
range with a
REF
REF
when
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The ideal code transitions occur midway between successive
integer LSB values (that is, 1/2 LSB, 3/2 LSB, 5/2 LSB, … ,
FS − 3/2 LSB). The ideal input/output transfer characteristic
is shown in Figure 39.
Fully Differential Mode
The amplitude of the differential signal is the difference between
the signals applied to the V
is, V
signal is, therefore, –V
regardless of the common mode (CM). The common mode is
the average of the two signals, for example, (V
is, therefore, the voltage that the two inputs are centered on.
This results in the span of each input being CM ± V
voltage has to be set up externally, and its range varies with V
(see the Driving the Analog Inputs section).
The output coding is twos complement in fully differential mode
with 1 LSB = 2 V
V
to the right. This allows the result in ADCDAT to be declared as a
signed integer when writing C code. The designed code
transitions occur midway between successive integer LSB values
(that is, 1/2 LSB, 3/2 LSB, 5/2 LSB, … , FS − 3/2 LSB). The ideal
input/output transfer characteristic is shown in Figure 40.
ADuC7019/20/21/22/24/25/26/27/28/29
Figure 39. ADC Transfer Function in Pseudo Differential or Single-Ended Mode
REF
SIGN
BIT
IN+
0 1111 1111 1110
0 1111 1111 1100
0 1111 1111 1010
0 0000 0000 0010
0 0000 0000 0000
1 1111 1111 1110
1 0000 0000 0100
1 0000 0000 0010
1 0000 0000 0000
= 2.5 V. The output result is ±11 bits, but this is shifted by 1
1111 1111 1111
1111 1111 1110
1111 1111 1101
1111 1111 1100
0000 0000 0011
0000 0000 0010
0000 0000 0001
0000 0000 0000
− V
Figure 40. ADC Transfer Function in Differential Mode
IN–
). The maximum amplitude of the differential
REF
0V
–V
/4096 or 2 × 2.5 V/4096 = 1.22 mV when
REF
1LSB
1LSB =
REF
1LSB =
+ 1LSB
to +V
IN+
2 × V
VOLTAGE INPUT (V
4096
4096
FS
and V
REF
REF
VOLTAGE INPUT
p-p (that is, 2 × V
0LSB
IN–
input voltage pins (that
IN
+ – V
IN+
IN
+V
+FS – 1LSB
+ V
–)
REF
REF
REF
IN–
– 1LSB
/2. This
). This is
)/2, and
REF