ADUC7024BSTZ62 Analog Devices Inc, ADUC7024BSTZ62 Datasheet
ADUC7024BSTZ62
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ADUC7024BSTZ62 Summary of contents
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FEATURES Analog I/O Multichannel, 12-bit, 1 MSPS ADC ADC channels Fully differential and single-ended modes analog input range REF 12-bit voltage output DACs DAC outputs available On-chip voltage ...
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ADuC7019/20/21/22/24/25/26/27/28 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 3 General Description ......................................................................... 4 Detailed Block Diagram .............................................................. 5 Specifications..................................................................................... 6 Timing Specifications .................................................................. 9 Absolute Maximum Ratings.......................................................... 16 ESD Caution................................................................................ 16 ...
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REVISION HISTORY 3/07—Rev Rev. B Added ADuC7028 Part ..................................................... Universal Updated Format.................................................................. Universal Changes to Figure 2...........................................................................5 Changes to Table 1 ............................................................................6 Changes to ADuC7026/ADuC7027 Section ...............................23 Changes to Figure 21 ......................................................................28 Changes to Figure 32 Caption .......................................................30 ...
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ADuC7019/20/21/22/24/25/26/27/28 GENERAL DESCRIPTION The ADuC7019/20/21/22/24/25/26/27/28 are fully integrated, 1 MSPS, 12-bit data acquisition systems incorporating high performance multichannel ADCs, 16-bit/32-bit MCUs, and Flash/EE memory on a single chip. The ADC consists single-ended inputs. An additional four ...
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DETAILED BLOCK DIAGRAM ADC0 77 ADC1 78 12-BIT SAR ADC2/CMP0 79 ADC 1MSPS ADC3/CMP1 80 ADC4 1 ADC5 2 ADC6 3 MUX ADC7 4 ADC8 5 ADC9 6 ADC10 7 ADC11 76 TEMP SENSOR ...
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ADuC7019/20/21/22/24/25/26/27/28 SPECIFICATIONS AV = IOV = 2 3 2.5 V internal reference REF Table 1. Parameter ADC CHANNEL SPECIFICATIONS ADC Power-Up Time Accuracy Resolution Integral Nonlinearity 3, 4 Differential ...
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Parameter DAC AC CHARACTERISTICS Voltage Output Settling Time Digital-to-Analog Glitch Energy COMPARATOR Input Offset Voltage Input Bias Current Input Voltage Range Input Capacitance 4, 6 Hysteresis Response Time TEMPERATURE SENSOR Voltage Output at 25°C Voltage TC Accuracy POWER SUPPLY MONITOR ...
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ADuC7019/20/21/22/24/25/26/27/28 Parameter START-UP TIME At Power-On From Pause/Nap Mode From Sleep Mode From Stop Mode PROGRAMMABLE LOGIC ARRAY (PLA) Pin Propagation Delay Element Propagation Delay 12, 13 POWER REQUIREMENTS Power Supply Voltage Range AV to AGND and IOV to IOGND ...
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TIMING SPECIFICATIONS Table 2. External Memory Write Cycle Parameter Min CLK t 0 MS_AFTER_CLKH t 4 ADDR_AFTER_CLKH t AE_H_AFTER_MS HOLD_ADDR_AFTER_AE_L t HOLD_ADDR_BEFORE_WR_L t WR_L_AFTER_AE_L t 8 DATA_AFTER_WR_L WR_H_AFTER_CLKH t HOLD_DATA_AFTER_WR_H t BEN_AFTER_AE_L t ...
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ADuC7019/20/21/22/24/25/26/27/28 Table 3. External Memory Read Cycle Parameter Min CLK 1/MD Clock t 4 MS_AFTER_CLKH t 4 ADDR_AFTER_CLKH t AE_H_AFTER_MS HOLD_ADDR_AFTER_AE_L t RD_L_AFTER_AE_L t 0 RD_H_AFTER_CLKH DATA_BEFORE_RD_H t 8 DATA_AFTER_RD_H t RELEASE_MS_AFTER_RD_H CLK ...
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Table Timing in Fast Mode (400 kHz) Parameter Description t SCLOCK low pulse width L t SCLOCK high pulse width H t Start condition hold time SHD t Data setup time DSU t Data hold time ...
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ADuC7019/20/21/22/24/25/26/27/28 Table 6. SPI Master Mode Timing (PHASE Mode = 1) Parameter Description t SCLOCK low pulse width SL t SCLOCK high pulse width SH t Data output valid after SCLOCK edge DAV t Data input setup time before SCLOCK ...
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Table 6. SPI Master Mode Timing (PHASE Mode = 0) Parameter Description t SCLOCK low pulse width SL t SCLOCK high pulse width SH t Data output valid after SCLOCK edge DAV t Data output setup before SCLOCK edge DOSU ...
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ADuC7019/20/21/22/24/25/26/27/28 Table 7. SPI Slave Mode Timing (PHASE Mode = 1) Parameter Description SCLOCK edge CS t SCLOCK low pulse width SL t SCLOCK high pulse width SH t Data output valid after SCLOCK edge DAV ...
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Table 8. SPI Slave Mode Timing (PHASE Mode = 0) Parameter Description SCLOCK edge CS t SCLOCK low pulse width SL t SCLOCK high pulse width SH t Data output valid after SCLOCK edge DAV t ...
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ADuC7019/20/21/22/24/25/26/27/28 ABSOLUTE MAXIMUM RATINGS AGND = REFGND = DACGND = GND T = 25°C, unless otherwise noted. A Table 9. Parameter AV to IOV DD DD AGND to DGND IOV to IOGND AGND DD DD Digital Input Voltage ...
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PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS ADuC7019/ADuC7020/ADuC7021/ADuC7022 BM/P0.0/CMP Figure 10. 40-Lead LFCSP_VQ Pin Configuration (ADuC7019/ADuC7020) BM/P0.0/CMP ADC3/CMP1 1 PIN 1 ADC4 2 INDICATOR GND 3 REF DAC0/ADC12 4 ADuC7019/ DAC1/ADC13 5 ADuC7020 DAC2/ADC14 6 TOP VIEW DAC3/ADC15 7 (Not to Scale) ...
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ADuC7019/20/21/22/24/25/26/27/28 BM/P0.0/CMP P0.6/T1/MRST/PLAO[3] Table 10. Pin Function Descriptions (ADuC7019/ADuC7020/ADuC7021/ADuC7022) Pin No. 7019/7020 7021 7022 Mnemonic ADC0 ADC1 ADC2/CMP0 ADC3/CMP1 ADC4 ‒ ADC5 ‒ ...
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Pin No. 7019/7020 7021 7022 Mnemonic P0.6/T1/MRST/PLAO[ TCK TDO IOGND IOV DGND P0.3/TRST/ADC ...
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ADuC7019/20/21/22/24/25/26/27/28 ADuC7024/ADuC7025 BM/P0.0/CMP P0.6/T1/MRST/PLAO[3] Figure 13. 64-Lead LFCSP_VQ Pin Configuration (ADuC7024/ADuC7025) BM/P0.0/CMP P0.6/T1/MRST/PLAO[3] ADC4 1 PIN 1 ADC5 2 INDICATOR ADC6 3 ADC7 4 ADC8 5 ADuC7024/ ADC9 6 GND 7 ADuC7025 REF ADCNEG 8 TOP VIEW DAC0/ADC12 9 (Not ...
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Table 11. Pin Function Descriptions (ADuC7024/ADuC7025 64-Lead LFCSP_VQ and 64-Lead LQFP) Pin No. Mnemonic 1 ADC4 2 ADC5 3 ADC6 4 ADC7 5 ADC8 6 ADC9 7 GND REF 8 ADCNEG 9 DAC0/ADC12 10 DAC1/ADC13 11 TMS 12 TDI 13 ...
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ADuC7019/20/21/22/24/25/26/27/28 Pin No. Mnemonic 37 P3.6/PWM /PLAI[14] TRIP 38 P3.7/PWM /PLAI[15] SYNC 39 P1.7/SPM7/PLAO[0] 40 P1.6/SPM6/PLAI[6] 41 IOGND 42 IOV DD 43 P4.0/PLAO[8] 44 P4.1/PLAO[9] 45 P1.5/SPM5/PLAI[5]/IRQ3 46 P1.4/SPM4/PLAI[4]/IRQ2 47 P1.3/SPM3/PLAI[3] 48 P1.2/SPM2/PLAI[2] 49 P1.1/SPM1/PLAI[1] 50 P1.0/T1/SPM0/PLAI[0] 51 P4.2/PLAO[10] 52 ...
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ADuC7026/ADuC7027 ADC4 ADC5 ADC6 ADC7 ADC8 ADC9 ADC10 GND REF ADCNEG DAC0/ADC12 DAC1/ADC13 DAC2/ADC14 DAC3/ADC15 TMS TDI P0.1/PWM2 /BLE H P2.3/AE P4.6/AD14/PLAO[14] P4.7/AD15/PLAO[15] BM/P0.0/CMP /PLAI[7]/MS0 OUT Table 12. Pin Function Descriptions (ADuC7026/ADuC7027) Pin No. Mnemonic 1 ADC4 2 ADC5 3 ...
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ADuC7019/20/21/22/24/25/26/27/28 Pin No. Mnemonic 15 TDI 16 P0.1/PWM2 /BLE H 17 P2.3/AE 18 P4.6/AD14/PLAO[14] 19 P4.7/AD15/PLAO[15] 20 BM/P0.0/CMP /PLAI[7]/MS0 OUT 21 P0.6/T1/MRST/PLAO[3] 22 TCK 23 TDO 24 P0.2/PWM2 /BHE L 25 IOGND 26 IOV DGND ...
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Pin No. Mnemonic 46 P3.6/AD6/PWM /PLAI[14] TRIP 47 P3.7/AD7/PWM /PLAI[15] SYNC 48 P2.7/PWM1 /MS3 L 49 P2.1/WS/PWM0 /PLAO[ P2.2/RS/PWM0 /PLAO[ P1.7/SPM7/PLAO[0] 52 P1.6/SPM6/PLAI[6] 53 IOGND 54 IOV DD 55 P4.0/AD8/PLAO[8] 56 P4.1/AD9/PLAO[9] 57 P1.5/SPM5/PLAI[5]/IRQ3 58 P1.4/SPM4/PLAI[4]/IRQ2 ...
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ADuC7019/20/21/22/24/25/26/27/28 ADuC7028 Table 13. Pin Function Descriptions (ADuC7028) Ball No. Mnemonic A1 ADC3/CMP1 A2 DACV AGND A5 DACGND A6 P4.2/PLAO[10] A7 P1.1/SPM1/PLAI[1] A8 P1.2/SPM2/PLAI[2] B1 ADC4 B2 ADC2/CMP0 B3 ADC1 B4 DAC REF B5 V ...
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Ball No. Mnemonic D7 P1.6/SPM6/PLAI[6] D8 IOV DD E1 DAC3 E2 DAC2 E3 DAC1 E4 P3.0/PWM0 /PLAI[ P3.2/PWM1 /PLAI[10 P1.5/SPM5/PLAI[5]/IRQ3 E7 P3.7/PWM /PLAI[15] SYNC E8 XCLKI F1 P4.6/PLAO[14] F2 TDI F3 DAC0s F4 P3.1/PWM0 /PLAI[9] L ...
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ADuC7019/20/21/22/24/25/26/27/28 TYPICAL PERFORMANCE CHARACTERISTICS 1 774kSPS S 0.8 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 –1.0 0 1000 2000 ADC CODES Figure 17. Typical INL Error 1 1MSPS S 0.8 0.6 0.4 0.2 ...
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BIN Figure 23. Code Histogram Plot 774 kSPS SNR = 69.3dB, –20 THD = –80.8dB, PHSN = –83.4dB –40 –60 –80 –100 ...
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ADuC7019/20/21/22/24/25/26/27/28 12.05 12.00 11.95 11.90 11.85 11.80 11.75 11.70 11.65 11.60 11.55 – TEMPERATURE (°C) Figure 29. Current Consumption vs. Temperature @ 7.85 7.80 7.75 7.70 7.65 7.60 7.55 7.50 7.45 7.40 – ...
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TERMINOLOGY ADC SPECIFICATIONS Integral Nonlinearity (INL) The maximum deviation of any code from a straight line passing through the endpoints of the ADC transfer function. The endpoints of the transfer function are zero scale, a point ½ LSB below the ...
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ADuC7019/20/21/22/24/25/26/27/28 OVERVIEW OF THE ARM7TDMI CORE The ARM7® core is a 32-bit reduced instruction set computer (RISC). It uses a single 32-bit bus for instruction and data. The length of the data can be 8 bits, 16 bits ...
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More information relative to the programmer’s model and the ARM7TDMI core architecture can be found in the following materials from ARM: • DDI0029G, ARM7TDMI Technical Reference Manual • DDI-0100, ARM Architecture Reference Manual INTERRUPT LATENCY The worst-case latency for a ...
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ADuC7019/20/21/22/24/25/26/27/28 MEMORY ORGANIZATION The ADuC7019/20/21/22/24/25/26/27/28 incorporate two separate blocks of memory SRAM and on-chip Flash/EE memory on-chip Flash/EE memory is available to the user, and the remaining 2 kB are reserved ...
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PWM 0xFFFFFC00 0xFFFFF820 FLASH CONTROL INTERFACE 0xFFFFF800 0xFFFFF46C GPIO 0xFFFFF400 0xFFFF0B54 PLA 0xFFFF0B00 0xFFFF0A14 SPI 0xFFFF0A00 0xFFFF0948 0xFFFF0900 0xFFFF0848 0xFFFF0800 0xFFFF0730 UART 0xFFFF0700 0xFFFF0620 DAC 0xFFFF0600 0xFFFF0538 ADC 0xFFFF0500 0xFFFF0490 BAND GAP ...
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ADuC7019/20/21/22/24/25/26/27/28 Access Address Name Byte Type Reference Address Base = 0xFFFF0480 0x048C REFCON 1 R/W ADC Address Base = 0xFFFF0500 0x0500 ADCCON 2 R/W 0x0504 ADCCP 1 R/W 0x0508 ADCCN 1 R/W 0x050C ADCSTA 1 R 0x0510 ADCDAT 4 R ...
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Access Address Name Byte Type PLA Base Address = 0xFFFF0B00 0x0B00 PLAELM0 2 R/W 0x0B04 PLAELM1 2 R/W 0x0B08 PLAELM2 2 R/W 0x0B0C PLAELM3 2 R/W 0x0B10 PLAELM4 2 R/W 0x0B14 PLAELM5 2 R/W 0x0B18 PLAELM6 2 R/W 0x0B1C PLAELM7 ...
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ADuC7019/20/21/22/24/25/26/27/28 ADC CIRCUIT OVERVIEW The analog-to-digital converter (ADC) incorporates a fast, multichannel, 12-bit ADC. It can operate from 2 3.6 V supplies and is capable of providing a throughput MSPS when the clock source ...
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TYPICAL OPERATION Once configured via the ADC control and channel selection registers, the ADC converts the analog input and provides a 12-bit result in the ADC data register. The top 4 bits are the sign bits. The 12-bit result is ...
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ADuC7019/20/21/22/24/25/26/27/28 Table 15. ADCCON MMR Bit Designations Bit Value Description 15:13 Reserved. 12:10 ADC clock speed. 000 fADC/1. This divider is provided to obtain 1 MSPS ADC with an external clock <41.78 MHz. 001 fADC/2 (default value). 010 fADC/4. 011 ...
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Table 17. ADCCN MMR Bit Designation Bit Value Description 7:5 Reserved. 4:0 Negative channel selection bits. 00000 ADC0. 00001 ADC1. 00010 ADC2. 00011 ADC3. 00100 ADC4. 00101 ADC5. 00110 ADC6. 00111 ADC7. 01000 ADC8. 01001 ADC9. 01010 ADC10. 01011 ADC11. ...
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ADuC7019/20/21/22/24/25/26/27/28 Pseudo Differential Mode In pseudo differential mode, Channel− is linked to the V of the ADuC7019/20/21/22/24/25/26/27/28. SW2 switches between A (Channel−) and REF IN− connected to ground or a low voltage. The input signal on ...
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Table 18. V Ranges Min V Max DD REF CM CM 3.3 V 2.5 V 1.25 V 2.05 V 2.048 V 1.024 V 2.276 V 1.25 V 0.75 V 2.55 V 3.0 V 2.5 V 1.25 ...
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ADuC7019/20/21/22/24/25/26/27/28 NONVOLATILE FLASH/EE MEMORY The ADuC7019/20/21/22/24/25/26/27/28 incorporate Flash/EE memory technology on-chip to provide the user with nonvolatile, in-circuit reprogrammable memory space. Like EEPROM, flash memory can be programmed in-system at a byte level, although it must first be erased. The ...
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SECURITY The Flash/EE memory available to the user can be read and write protected. Bit 31 of the FEEPRO/FEEHIDE MMR (see Table 23) protects the 62 kB from being read through JTAG programming mode. The other 31 ...
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ADuC7019/20/21/22/24/25/26/27/28 FEECON Register Name Address Default Value FEECON 0xFFFFF808 0x07 FEECON is an 8-bit command register. The commands are described in Table 22. Table 22. Command Codes in FEECON Code Command Description 1 0x00 Null Idle State. 1 0x01 Single ...
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EXECUTION TIME FROM SRAM AND FLASH/EE Execution from SRAM Fetching instructions from SRAM takes one clock cycle as the access time of the SRAM and a clock cycle minimum. However, if the instruction involves ...
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ADuC7019/20/21/22/24/25/26/27/28 Reset Operation There are four kinds of reset: external, power-on, watchdog expiation, and software force. The RSTSTA register indicates the source of the last reset, and RSTCLR allows clearing of the RSTSTA register. These registers can be used during ...
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OTHER ANALOG PERIPHERALS DAC The ADuC7019/20/21/22/24/25/26/27/28 incorporate two, three, or four, 12-bit voltage output DACs on-chip, depending on the model. Each DAC has a rail-to-rail voltage output buffer capable of driving 5 kΩ/100 pF. Each DAC has three selectable ranges: ...
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ADuC7019/20/21/22/24/25/26/27/28 Linearity degradation near ground and V ration of the output amplifier, and a general representation of its effects (neglecting offset and gain error) is illustrated in Figure 53. The dotted line in Figure 53 indicates the ideal transfer function, ...
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Comparator Interface The comparator interface consists of a 16-bit MMR, CMPCON, which is described in Table 30. CMPCON Register Name Address Default Value CMPCON 0xFFFF0444 0x0000 Table 30. CMPCON MMR Bit Descriptions Bit Value Name Description 15:11 Reserved. 10 CMPEN ...
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ADuC7019/20/21/22/24/25/26/27/28 Example source code: T2LD = 5; TCON = 0x480; while ((T2VAL == t2val_old) || (T2VAL > 3)) //ensures timer value loaded IRQEN = 0x10; //enable T2 interrupt PLLKEY1 = 0xAA; PLLCON = 0x01; PLLKEY2 = 0x55; POWKEY1 = 0x01; ...
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MMRs and Keys The operating mode, clocking mode, and programmable clock divider are controlled via two MMRs, PLLCON (see Table 33) and POWCON (see Table 34). PLLCON controls the operating mode of the clock system, while POWCON controls the core ...
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ADuC7019/20/21/22/24/25/26/27/28 DIGITAL PERIPHERALS 3-PHASE PWM Each ADuC7019/20/21/22/24/25/26/27/28 provides a flexible and programmable, 3-phase pulse-width modulation (PWM) waveform generator. It can be programmed to generate the required switching patterns to drive a 3-phase voltage source inverter for ac induction motor control ...
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DESCRIPTION OF THE PWM BLOCK A functional block diagram of the PWM controller is shown in Figure 57. The generation of the six output PWM signals on Pin PWM0 to Pin PWM2 is controlled by the following four H L ...
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ADuC7019/20/21/22/24/25/26/27/28 The PWMDAT1 register is a 10-bit register with a maximum value of 0x3FF (= 1023), which corresponds to a maximum programmed dead time 1023 × 2 × 1023 × 2 × 24 ×10 D(max) ...
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Both switching edges are moved by an equal amount (PWMDAT1 × preserve the symmetrical output CORE patterns. Also shown is the PWMSYNC pulse and Bit 0 of the PWMSTA register, which indicates whether operation is in the ...
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ADuC7019/20/21/22/24/25/26/27/28 Output Control Unit The operation of the output control unit is controlled by the 9-bit read/write PWMEN register. This register controls two distinct features of the output control unit that are directly useful in the control of electronic counter ...
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The GDCLK value can range from 0 to 255, corresponding to a programmable chopping frequency rate of 40.8 kHz to 10.44 MHz for a 41.78 MHz core frequency. The gate drive features must be programmed before operation of the PWM ...
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ADuC7019/20/21/22/24/25/26/27/28 PWMCFG Register Name Address Default Value PWMCFG 0xFFFFFC10 0x0000 PWMCFG is a gate chopping register. Table 38. PWMCFG MMR Bit Descriptions Bit Name Description 15:10 – Reserved. 9 CHOPLO Low-Side Gate Chopping Enable Bit. 8 CHOPHI High-Side Gate Chopping ...
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Table 40. GPIO Pin Function Descriptions Configuration Port Pin P0.0 GPIO CMP P0.1 GPIO PWM2 H P0.2 GPIO PWM2 L P0.3 GPIO TRST P0.4 GPIO/IRQ0 PWM TRIP P0.5 GPIO/IRQ1 ADC BUSY P0.6 GPIO/T1 MRST P0.7 GPIO ECLK/XCLK ...
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ADuC7019/20/21/22/24/25/26/27/28 GPxDAT Registers Name Address Default Value GP0DAT 0xFFFFF420 0x000000XX GP1DAT 0xFFFFF430 0x000000XX GP2DAT 0xFFFFF440 0x000000XX GP3DAT 0xFFFFF450 0x000000XX GP4DAT 0xFFFFF460 0x000000XX GPxDAT are Port x configuration and data registers. They configure the direction of the GPIO pins of Port ...
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Normal 450 UART Baud Rate Generation The baud rate is a divided version of the core clock using the value in the COMDIV0 and COMDIV1 MMRs (16-bit value, DL MHz = Baud Rate × × × CD ...
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ADuC7019/20/21/22/24/25/26/27/28 Table 50. COMIID0 MMR Bit Descriptions Bit 2:1 Bit 0 Status Bits NINT Priority Definition 00 1 – No interrupt Receive Line Status Interrupt Receive Buffer Full Interrupt Transmit Buffer ...
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COMSTA1 Register Name Address Default Value COMSTA1 0xFFFF0718 0x00 COMSTA1 is a modem status register. Table 54. COMSTA1 MMR Bit Descriptions Bit Name Description 7 DCD Data Carrier Detect Ring Indicator. 5 DSR Data Set Ready. 4 CTS ...
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ADuC7019/20/21/22/24/25/26/27/28 Table 57. COMIID1 MMR Bit Descriptions Bit 3:1 Status Bit 0 Bits NINT Priority Definition 000 1 – No Interrupt. 110 0 2 Matching Network Address. 101 0 3 Address Transmitted, Buffer Empty. 011 0 1 Receive Line Status ...
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Table 59. SPISTA MMR Bit Descriptions Bit Description 7:6 Reserved. 5 SPIRX Data Register Overflow Status Bit. Set if SPIRX is overflowing. Cleared by reading SPIRX register. 4 SPIRX Data Register IRQ. Set automatically if Bit 3 or Bit 5 ...
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ADuC7019/20/21/22/24/25/26/27/ C-COMPATIBLE INTERFACES The ADuC7019/20/21/22/24/25/26/27/28 support two licensed I 2 interfaces. The I C interfaces are both implemented as a hardware master and a full slave interface. Because the two I identical, this data sheet describes only I2C0 ...
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Table 62. I2C0SSTA MMR Bit Descriptions Bit Value Description 31:15 Reserved. These bits should be written Start Decode Bit. Set by hardware if the device receives a valid start + matching address. Cleared ...
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ADuC7019/20/21/22/24/25/26/27/28 I2CxALT Registers Name Address Default Value I2C0ALT 0xFFFF0828 0x00 I2C1ALT 0xFFFF0928 0x00 I2CxALT are hardware general call ID registers used in slave mode. Table 63. I2C0CFG MMR Bit Descriptions Bit Description 31:5 Reserved. These bits should be written by ...
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I2CxDIV Registers Name Address Default Value I2C0DIV 0xFFFF0830 0x1F1F I2C1DIV 0xFFFF0930 0x1F1F I2CxDIV are the clock divider registers. I2CxIDx Registers Name Address Default Value I2C0ID0 0xFFFF0838 0x00 I2C0ID1 0xFFFF083C 0x00 I2C0ID2 0xFFFF0840 0x00 I2C0ID3 0xFFFF0844 0x00 I2C1ID0 0xFFFF0938 0x00 I2C1ID1 ...
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ADuC7019/20/21/22/24/25/26/27/28 PROGRAMMABLE LOGIC ARRAY (PLA) Every ADuC7019/20/21/22/24/25/26/27/28 integrates a fully programmable logic array (PLA) that consists of two, independent but interconnected PLA blocks. Each block consists of eight PLA elements, giving each part a total of 16 PLA elements. Each ...
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PLACLK Register Name Address Default Value PLACLK 0xFFFF0B40 0x00 PLACLK is the clock selection for the flip-flops of Block 0 and Block 1. Note that the maximum frequency when using the GPIO pins as the clock input for the PLA ...
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ADuC7019/20/21/22/24/25/26/27/28 PLAADC Register Name Address Default Value PLAADC 0xFFFF0B48 0x00000000 PLAADC is the PLA source for the ADC start conversion signal. Table 70. PLAADC MMR Bit Descriptions Bit Value Description 31:5 Reserved. 4 ADC Start Conversion Enable Bit. Set by ...
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PROCESSOR REFERENCE PERIPHERALS INTERRUPT SYSTEM There are 23 interrupt sources on the ADuC7019/20/21/22/ 24/25/26/27/28 that are controlled by the interrupt controller. Most interrupts are generated from the on-chip peripherals, such as ADC and UART. Four additional interrupt sources are generated ...
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ADuC7019/20/21/22/24/25/26/27/28 FIQ The fast interrupt request (FIQ) is the exception signal to enter the FIQ mode of the processor provided to service data transfer or communication channel tasks with low latency. The FIQ interface is identical to the ...
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Timer0 (RTOS Timer) Timer0 is a general-purpose, 16-bit timer (count-down) with a programmable prescaler (see Figure 64). The prescaler source is the core clock frequency (HCLK) and can be scaled by factors of 1, 16, or 256. Timer0 can be ...
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ADuC7019/20/21/22/24/25/26/27/28 Table 76. T1CON MMR Bit Descriptions Bit Value Description 31:18 Reserved. 17 Event Select Bit. Set by user to enable time capture of an event. Cleared by user to disable time capture of an event. 16:12 Event Select Range, ...
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T2CLRI Register Name Address Default Value T2CLRI 0xFFFF034C 0xFF T2CLRI is an 8-bit register. Writing any value to this register clears the Timer2 interrupt. Timer3 (Watchdog Time) Timer3 has two modes of operation, normal mode and watchdog mode. The watchdog ...
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ADuC7019/20/21/22/24/25/26/27/28 Secure Clear Bit (Watchdog Mode Only) The secure clear bit is provided for a higher level of protection. When set, a specific sequential value must be written to T3CLRI to avoid a watchdog reset. The value is a sequence ...
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XMCFG Register Name Address Default Value XMCFG 0xFFFFF000 0x00 XMCFG is set enable external memory access. This must be set to 1 before any port pins function as external memory access pins. The port pins must also ...
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ADuC7019/20/21/22/24/25/26/27/28 MCLK AD16:0 MSx AE RS MCLK AD16:0 MSx AE RS Figure 71. External Memory Read Cycle with Address Hold and Bus Turn Cycles ADDRESS Figure 70. External Memory Read Cycle ADDRESS EXTRA ADDRESS HOLD TIME XMxPAR (BIT 10) BUS ...
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MCLK AD16:0 ADDRESS EXTRA ADDRESS HOLD TIME (BIT 10) MSx AE WS Figure 72. External Memory Write Cycle with Address and Write Hold Cycles MCLK AD16:0 ADDRESS MSx AE 1 ADDRESS WAIT STATE (BIT 14 TO BIT 12) WS Figure ...
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ADuC7019/20/21/22/24/25/26/27/28 HARDWARE DESIGN CONSIDERATIONS POWER SUPPLIES The ADuC7019/20/21/22/24/25/26/27/28 operational power supply voltage range is 2 3.6 V. Separate analog and digital power supply pins (AV and IOV kept relatively free of noisy digital signals ...
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GROUNDING AND BOARD LAYOUT RECOMMENDATIONS As with all high resolution data converters, special attention must be paid to grounding and PC board layout of the ADuC7019/20/21/22/24/25/26/27/28-based designs to achieve optimum performance from the ADCs and DAC. Although the parts have ...
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ADuC7019/20/21/22/24/25/26/27/28 POWER-ON RESET OPERATION An internal power-on reset (POR) is implemented on the ADuC7019/20/21/22/24/25/26/27/28. For LV typical, the internal POR holds the part in reset above 2. internal timer times out for typically 128 ms before ...
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DEVELOPMENT TOOLS PC-BASED TOOLS Four types of development systems are available for the ADuC7019/20/21/22/24/25/26/27/28 family: • The ADuC7026 QuickStart Plus is intended for new users who want to have a comprehensive hardware development environment. Because the ADuC7026 contains the superset ...
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ADuC7019/20/21/22/24/25/26/27/28 OUTLINE DIMENSIONS PIN 1 INDICATOR 12° MAX 1.00 0.85 0.80 SEATING PLANE BSC SQ PIN 1 INDICATOR 1.00 12° MAX 0.85 0.80 SEATING PLANE 6.00 BSC SQ 0.60 MAX 0.50 TOP BSC 5.75 VIEW BCS SQ 0.50 0.40 0.30 ...
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MAX 0.45 1.45 0.20 1.40 0.09 1.35 7° 3.5° 0° SEATING 0.08 PLANE COPLANARITY VIEW A ROTATED 90° CCW COMPLIANT TO JEDEC STANDARDS MS-026-BCD Figure 85. 64-Lead Low Profile Quad Flat Package [LQFP] Dimensions shown in millimeters ...
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ADuC7019/20/21/22/24/25/26/27/28 1.50 SQ DETAIL A * 1.40 1.31 1.16 ORDERING GUIDE ADC DAC Model Channels Channels 1 2 ADuC7019BCPZ62I ADuC7019BCPZ62I- ADuC7019BCPZ62IRL7 ADuC7020BCPZ62 1 ADuC7020BCPZ62- ...
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... ADC DAC Model Channels Channels 1 10 ADuC7022BCPZ62 1 ADuC7022BCPZ62- ADuC7022BCPZ62-RL7 ADuC7022BCPZ32 1 ADuC7022BCPZ32- ADuC7022BCPZ32-RL7 ADuC7024BCPZ62 1 ADuC7024BCPZ62- ADuC7024BCPZ62-RL7 ADuC7024BSTZ62 1 ADuC7024BSTZ62- ADuC7025BCPZ62 1 ADuC7025BCPZ62- ADuC7025BCPZ62-RL7 ADuC7025BCPZ32 1 ADuC7025BCPZ32- ADuC7025BCPZ32-RL7 ADuC7025BSTZ62 1 ADuC7025BSTZ62- ADuC7026BSTZ62 1, 3 ADuC7026BSTZ62- ADuC7026BSTZ62I 1, 3 ADuC7026BSTZ62I- ADuC7027BSTZ62 ADuC7027BSTZ62- ADuC7027BSTZ62I ADuC7027BSTZ62I-RL 1 ADuC7028BBCZ62 ADuC7028BBCZ62-RL 1 EVAL-ADuC7020MKZ 1 EVAL-ADuC7020QSZ 1 EVAL-ADuC7024QSZ 1 EVAL-ADuC7026QSZ ...
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ADuC7019/20/21/22/24/25/26/27/28 ADC DAC Model Channels Channels 1 EVAL-ADuC7026QSPZ 1 EVAL-ADuC7028QSZ RoHS Compliant Part. 2 One of the ADC channels is internally buffered. 3 Includes external memory interface. Purchase of licensed components of Analog Devices ...