AT91SAM7A3-AU Atmel, AT91SAM7A3-AU Datasheet - Page 592

• Manufacturer Part Number: AT91SAM7A3-AU
• Description: IC ARM7 MCU FLASH 256K 100LQFP
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM7A3-AU

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 60MHz
• Connectivity: CAN, I²C, MMC, SPI, SSC, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 62
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Controller Family/series: AT91SAM7xx
• No. Of I/o's: 62
• Ram Memory Size: 32KB
• Cpu Speed: 60MHz
• No. Of Timers: 3
• Rohs Compliant: Yes
• Package: 100LQFP
• Device Core: ARM7TDMI
• Family Name: 91S
• Maximum Speed: 60 MHz
• Operating Supply Voltage: 3.3 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 62
• Interface Type: CAN/SPI/I2S/TWI/USART/USB
• On-chip Adc: 2(8-chx10-bit)
• Number Of Timers: 3
• Processor Series: AT91SAMx
• Core: ARM7TDMI
• Data Ram Size: 32 KB
• Maximum Clock Frequency: 60 MHz
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP, AT91SAM7A3-EK
• Minimum Operating Temperature: - 40 C
• Cpu Family: 91S
• Device Core Size: 32b
• Frequency (max): 60MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 62
• Number Of Timers - General Purpose: 3
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 100
• Package Type: LQFP
• For Use With: AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9AT91SAM7A3-EK - KIT EVAL FOR AT91SAM7A3
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

xii
Version
6042E
AT91SAM7A3 Preliminary
Comments
Section 29., ”Universal Synchronous Asynchronous Receiver Transceiver (USART)”
last version, should be considered carefully. Updates include the following:
Section 29.5.4.1, ”ISO7816 Mode
Section 29.4.1, ”I/O
Table 29-3, “Binary and Decimal Values for Di”
page
Figure 29-24, ”IrDA Demodulator
Table 29-2, “Baud Rate Example (OVER =
Section 29.5.3.2, ”Asynchronous
synchronization mechanism.....”
Section 29.5.3.8, ”Receiver
Section 29.6.1, ”USART Control Register”
Section 29.6.6, ”USART Channel Status Register”
register
TC: added
Section 31.5.4, ”External Event/Trigger Conditions”
the compare register B is not used to generate waveforms and subsequently no IRQs.
The note
clarifies this condition.
Figure 31-2, ”Clock Chaining
PWM:
Section 33., ”USB Device Port
Updates include, but are not limited to the following:
Figure 33-2 on page 414
Section 33.4.1, ”USB Device Transceiver”
Section 33.5.1.2, ”USB Bus Transactions”
Section 33.5.1.3, ”USB Transfer Event
Section 33.5.2.2, ”Data IN Transaction”
Section 33.5.2, ”Handling Transactions with USB V2.0 Device
added.
Section 33.5.3, ”Controlling Device States”
Section 33.5.3.1, ”Not Powered State”
Section 33.6.2, ”UDP Global State
Section 33.6.10, ”UDP Endpoint Control and Status
Section 34., ”MultiMedia Card Interface (MCI)”
Figure 34-8, ”Read Functional Flow
Figure 34-9, ”Write Functional Flow
Figure 34-10, ”Multiple Write Functional Flow
Section 34.9.10, ”MCI Status
Section 34.9.10, ”MCI Status
ADC: editor use of variables in register tables added,
Section 35.5.7, ”ADC Timings”
In the Block Diagram,
differentiated.
280, DI and Fi properly referenced in titles.
Section 32.5.3.3, ”Changing the Duty Cycle or the
(1)
Table 31-1, “Timer Counter Clock Assignment,” on page
attached to the register bit description
Lines”, text concerning TXD line added.
Figure 35-1 on page
updated.
Time-out”, list of user options rewritten.
Selection”, added to demonstrate clock chaining.
Register”, update to descriptions of BLKE and NOTBUSY flags.
Register”, added reset information on DCRCE and DTOE bits.
(UDP)”, extensive update since last version, should be considered carefully.
In the Warning: “See ADC Characteristics....”, typo fixed
Receiver”, change to second sentence in fourth paragraph ”For the
Operations”, firgure modified.
Overview”, Clarification of PAR configuration.
Register”, updated.
Diagram”, update to flow chart.
Diagram”, update to flow chart.
and
Definitions”, updated with endpoint information.
endpoint use updated.
STTTO bit function related to TIMEOUT in US_CSR register.
and
updated.
Section 33.5.3.2, ”Entering Attached State”
475, dedicated and I/O line multiplexed analog inputs
0)”, last two lines of table removed.
section reworked.
Diagram”, added flow chart.
Section 33.4.2, ”VBUS Monitoring”
and
”EEVT: External Event Selection” on page 380
TIMEOUT bit function related to STTTO in US_CR
“....(EEVT = 0), TIOB is no longer used as an output and
Table 29-4, “Binary and Decimal Values for Fi,” on
Register”, updated.
Period”, Update to info on waveform generation.
Peripheral”, section reworked, warnings
357.
added.
extensive update since
have been added.
further
6042E–ATARM–14-Dec-06
Change
Request
Ref.
1552
rfo review
2942
3023
2470
2704
3342
1677
rfo rework +
2259,2542,
2544, 2826,
2905, 3014,
3048, 3055,
2462
2593
1749
2830
3052