AT91SAM7A3-AU Atmel, AT91SAM7A3-AU Datasheet - Page 128

• Manufacturer Part Number: AT91SAM7A3-AU
• Description: IC ARM7 MCU FLASH 256K 100LQFP
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM7A3-AU

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 60MHz
• Connectivity: CAN, I²C, MMC, SPI, SSC, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 62
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Controller Family/series: AT91SAM7xx
• No. Of I/o's: 62
• Ram Memory Size: 32KB
• Cpu Speed: 60MHz
• No. Of Timers: 3
• Rohs Compliant: Yes
• Package: 100LQFP
• Device Core: ARM7TDMI
• Family Name: 91S
• Maximum Speed: 60 MHz
• Operating Supply Voltage: 3.3 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 62
• Interface Type: CAN/SPI/I2S/TWI/USART/USB
• On-chip Adc: 2(8-chx10-bit)
• Number Of Timers: 3
• Processor Series: AT91SAMx
• Core: ARM7TDMI
• Data Ram Size: 32 KB
• Maximum Clock Frequency: 60 MHz
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP, AT91SAM7A3-EK
• Minimum Operating Temperature: - 40 C
• Cpu Family: 91S
• Device Core Size: 32b
• Frequency (max): 60MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 62
• Number Of Timers - General Purpose: 3
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 100
• Package Type: LQFP
• For Use With: AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9AT91SAM7A3-EK - KIT EVAL FOR AT91SAM7A3
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

22.7
22.7.1
22.7.1.1
22.7.1.2
22.7.1.3
22.7.1.4
128
Functional Description
AT91SAM7A3 Preliminary
Interrupt Source Control
Interrupt Source Mode
Interrupt Source Enabling
Interrupt Clearing and Setting
Interrupt Status
The Advanced Interrupt Controller independently programs each interrupt source. The SRC-
TYPE field of the corresponding AIC_SMR (Source Mode Register) selects the interrupt
condition of each source.
The internal interrupt sources wired on the interrupt outputs of the embedded peripherals can
be programmed either in level-sensitive mode or in edge-triggered mode. The active level of
the internal interrupts is not important for the user.
The external interrupt sources can be programmed either in high level-sensitive or low level-
sensitive modes, or in positive edge-triggered or negative edge-triggered modes.
Each interrupt source, including the FIQ in source 0, can be enabled or disabled by using the
command registers; AIC_IECR (Interrupt Enable Command Register) and AIC_IDCR (Inter-
rupt Disable Command Register). This set of registers conducts enabling or disabling in one
instruction. The interrupt mask can be read in the AIC_IMR register. A disabled interrupt does
not affect servicing of other interrupts.
All interrupt sources programmed to be edge-triggered (including the FIQ in source 0) can be
individually set or cleared by writing respectively the AIC_ISCR and AIC_ICCR registers.
Clearing or setting interrupt sources programmed in level-sensitive mode has no effect.
The clear operation is perfunctory, as the software must perform an action to reinitialize the
“memorization” circuitry activated when the source is programmed in edge-triggered mode.
However, the set operation is available for auto-test or software debug purposes. It can also
be used to execute an AIC-implementation of a software interrupt.
The AIC features an automatic clear of the current interrupt when the AIC_IVR (Interrupt Vec-
tor Register) is read. Only the interrupt source being detected by the AIC as the current
interrupt is affected by this operation.
clear reduces the operations required by the interrupt service routine entry code to reading the
AIC_IVR. Note that the automatic interrupt clear is disabled if the interrupt source has the Fast
Forcing feature enabled as it is considered uniquely as a FIQ source. (For further details,
“Fast Forcing” on page
The automatic clear of the interrupt source 0 is performed when AIC_FVR is read.
For each interrupt, the AIC operation originates in AIC_IPR (Interrupt Pending Register) and
its mask in AIC_IMR (Interrupt Mask Register). AIC_IPR enables the actual activity of the
sources, whether masked or not.
The AIC_ISR register reads the number of the current interrupt (see
page
the processor.
Each status referred to above can be used to optimize the interrupt handling of the systems.
132) and the register AIC_CISR gives an image of the signals nIRQ and nFIQ driven on
136.)
(See “Priority Controller” on page
”Priority Controller” on
132.) The automatic
6042E–ATARM–14-Dec-06
See