AT91SAM7A3-AU Atmel, AT91SAM7A3-AU Datasheet - Page 504

• Manufacturer Part Number: AT91SAM7A3-AU
• Description: IC ARM7 MCU FLASH 256K 100LQFP
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM7A3-AU

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 60MHz
• Connectivity: CAN, I²C, MMC, SPI, SSC, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 62
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Controller Family/series: AT91SAM7xx
• No. Of I/o's: 62
• Ram Memory Size: 32KB
• Cpu Speed: 60MHz
• No. Of Timers: 3
• Rohs Compliant: Yes
• Package: 100LQFP
• Device Core: ARM7TDMI
• Family Name: 91S
• Maximum Speed: 60 MHz
• Operating Supply Voltage: 3.3 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 62
• Interface Type: CAN/SPI/I2S/TWI/USART/USB
• On-chip Adc: 2(8-chx10-bit)
• Number Of Timers: 3
• Processor Series: AT91SAMx
• Core: ARM7TDMI
• Data Ram Size: 32 KB
• Maximum Clock Frequency: 60 MHz
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP, AT91SAM7A3-EK
• Minimum Operating Temperature: - 40 C
• Cpu Family: 91S
• Device Core Size: 32b
• Frequency (max): 60MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 62
• Number Of Timers - General Purpose: 3
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 100
• Package Type: LQFP
• For Use With: AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9AT91SAM7A3-EK - KIT EVAL FOR AT91SAM7A3
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

36.6.4.2
6042E–ATARM–14-Dec-06
Fault Confinement
Error Detection
There are five different error types that are not mutually exclusive. Each error concerns only
specific fields of the CAN data frame (refer to the Bosch CAN specification for their
correspondence):
To distinguish between temporary and permanent failures, every CAN controller has two error
counters: REC (Receive Error Counter) and TEC (Transmit Error Counter). The counters are
incremented upon detected errors and respectively are decremented upon correct transmis-
sions or receptions. Depending on the counter values, the state of the node changes: the
initial state of the CAN controller is Error Active, meaning that the controller can send Error
Active flags. The controller changes to the Error Passive state if there is an accumulation of
errors. If the CAN controller fails or if there is an extreme accumulation of errors, there is a
state transition to Bus Off.
Figure 36-7. Line Error Mode
• CRC error (CERR bit in the CAN_SR register): With the CRC, the transmitter calculates a
• Bit-stuffing error (SERR bit in the CAN_SR register): If a node detects a sixth consecutive
• Bit error (BERR bit in CAN_SR register): A bit error occurs if a transmitter sends a
• Form Error (FERR bit in the CAN_SR register): If a transmitter detects a dominant bit in
• Acknowledgment error (AERR bit in the CAN_SR register): The transmitter checks the
checksum for the CRC bit sequence from the Start of Frame bit until the end of the Data
Field. This CRC sequence is transmitted in the CRC field of the Data or Remote Frame.
equal bit level during the bit-stuffing area of a frame, it generates an Error Frame starting
with the next bit-time.
dominant bit but detects a recessive bit on the bus line, or if it sends a recessive bit but
detects a dominant bit on the bus line. An error frame is generated and starts with the next
bit time.
one of the fix-formatted segments CRC Delimiter, ACK Delimiter or End of Frame, a form
error has occurred and an error frame is generated.
Acknowledge Slot, which is transmitted by the transmitting node as a recessive bit,
contains a dominant bit. If this is the case, at least one other node has received the frame
correctly. If not, an Acknowledge Error has occurred and the transmitter will start in the next
bit-time an Error Frame transmission.
REC > 127
TEC > 127
or
PASSIVE
ERROR
ERROR
ACTIVE
TEC > 255
Init
REC < 127
TEC < 127
and
AT91SAM7A3 Preliminary
128 occurences of 11 consecutive recessive bits
BUS OFF
CAN controller reset
or
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