AT91SAM7A3-AU Atmel, AT91SAM7A3-AU Datasheet - Page 135

• Manufacturer Part Number: AT91SAM7A3-AU
• Description: IC ARM7 MCU FLASH 256K 100LQFP
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM7A3-AU

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 60MHz
• Connectivity: CAN, I²C, MMC, SPI, SSC, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 62
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Controller Family/series: AT91SAM7xx
• No. Of I/o's: 62
• Ram Memory Size: 32KB
• Cpu Speed: 60MHz
• No. Of Timers: 3
• Rohs Compliant: Yes
• Package: 100LQFP
• Device Core: ARM7TDMI
• Family Name: 91S
• Maximum Speed: 60 MHz
• Operating Supply Voltage: 3.3 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 62
• Interface Type: CAN/SPI/I2S/TWI/USART/USB
• On-chip Adc: 2(8-chx10-bit)
• Number Of Timers: 3
• Processor Series: AT91SAMx
• Core: ARM7TDMI
• Data Ram Size: 32 KB
• Maximum Clock Frequency: 60 MHz
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP, AT91SAM7A3-EK
• Minimum Operating Temperature: - 40 C
• Cpu Family: 91S
• Device Core Size: 32b
• Frequency (max): 60MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 62
• Number Of Timers - General Purpose: 3
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 100
• Package Type: LQFP
• For Use With: AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9AT91SAM7A3-EK - KIT EVAL FOR AT91SAM7A3
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

22.7.4
22.7.4.1
22.7.4.2
22.7.4.3
22.7.4.4
6042E–ATARM–14-Dec-06
Fast Interrupt
Fast Interrupt Source
Fast Interrupt Control
Fast Interrupt Vectoring
Fast Interrupt Handlers
The interrupt source 0 is the only source which can raise a fast interrupt request to the proces-
sor except if fast forcing is used. The interrupt source 0 is generally connected to a FIQ pin of
the product, either directly or through a PIO Controller.
The fast interrupt logic of the AIC has no priority controller. The mode of interrupt source 0 is
programmed with the AIC_SMR0 and the field PRIOR of this register is not used even if it
reads what has been written. The field SRCTYPE of AIC_SMR0 enables programming the
fast interrupt source to be positive-edge triggered or negative-edge triggered or high-level sen-
sitive or low-level sensitive
Writing 0x1 in the AIC_IECR (Interrupt Enable Command Register) and AIC_IDCR (Interrupt
Disable Command Register) respectively enables and disables the fast interrupt. The bit 0 of
AIC_IMR (Interrupt Mask Register) indicates whether the fast interrupt is enabled or disabled.
The fast interrupt handler address can be stored in AIC_SVR0 (Source Vector Register 0).
The value written into this register is returned when the processor reads AIC_FVR (Fast Vec-
tor Register). This offers a way to branch in one single instruction to the interrupt handler, as
AIC_FVR is mapped at the absolute address 0xFFFF F104 and thus accessible from the ARM
fast interrupt vector at address 0x0000 001C through the following instruction:
When the processor executes this instruction it loads the value read in AIC_FVR in its pro-
gram counter, thus branching the execution on the fast interrupt handler. It also automatically
performs the clear of the fast interrupt source if it is programmed in edge-triggered mode.
This section gives an overview of the fast interrupt handling sequence when using the AIC. It
is assumed that the programmer understands the architecture of the ARM processor, and
especially the processor interrupt modes and associated status bits.
Assuming that:
When nFIQ is asserted, if the bit “F” of CPSR is 0, the sequence is:
1. The Advanced Interrupt Controller has been programmed, AIC_SVR0 is loaded with
2. The Instruction at address 0x1C (FIQ exception vector address) is required to vector
3. The user does not need nested fast interrupts.
1. The CPSR is stored in SPSR_fiq, the current value of the program counter is loaded
2. The ARM core enters FIQ mode.
3. When the instruction loaded at address 0x1C is executed, the program counter is
LDR
LDR PC, [PC, # -&F20]
the fast interrupt service routine address, and the interrupt source 0 is enabled.
the fast interrupt:
in the FIQ link register (R14_FIQ) and the program counter (R15) is loaded with
0x1C. In the following cycle, during fetch at address 0x20, the ARM core adjusts
R14_fiq, decrementing it by four.
loaded with the value read in AIC_FVR. Reading the AIC_FVR has effect of automat-
PC,[PC,# -&F20]
AT91SAM7A3 Preliminary
135