AT91SAM7A3-AU Atmel, AT91SAM7A3-AU Datasheet - Page 104

• Manufacturer Part Number: AT91SAM7A3-AU
• Description: IC ARM7 MCU FLASH 256K 100LQFP
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM7A3-AU

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 60MHz
• Connectivity: CAN, I²C, MMC, SPI, SSC, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 62
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Controller Family/series: AT91SAM7xx
• No. Of I/o's: 62
• Ram Memory Size: 32KB
• Cpu Speed: 60MHz
• No. Of Timers: 3
• Rohs Compliant: Yes
• Package: 100LQFP
• Device Core: ARM7TDMI
• Family Name: 91S
• Maximum Speed: 60 MHz
• Operating Supply Voltage: 3.3 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 62
• Interface Type: CAN/SPI/I2S/TWI/USART/USB
• On-chip Adc: 2(8-chx10-bit)
• Number Of Timers: 3
• Processor Series: AT91SAMx
• Core: ARM7TDMI
• Data Ram Size: 32 KB
• Maximum Clock Frequency: 60 MHz
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP, AT91SAM7A3-EK
• Minimum Operating Temperature: - 40 C
• Cpu Family: 91S
• Device Core Size: 32b
• Frequency (max): 60MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 62
• Number Of Timers - General Purpose: 3
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 100
• Package Type: LQFP
• For Use With: AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9AT91SAM7A3-EK - KIT EVAL FOR AT91SAM7A3
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Figure 20-4. Code Read Optimization in Thumb Mode for FWS = 3
Note:
20.2.3
20.2.4
104
ARM Request (16-bit)
Buffer (32 bits)
Flash Access
Data To ARM
Master Clock
When FWS is equal to 2 or 3, in case of sequential reads, the first access takes FWS cycles, the second access one cycle, the
third access FWS cycles, the fourth access one cycle, etc.
Code Fetch
AT91SAM7A3 Preliminary
Write Operations
Flash Commands
@Byte 0
3 Wait State Cycles
The internal memory area reserved for the Embedded Flash can also be written through a
write-only latch buffer. Write operations take into account only the 8 lowest address bits and
thus wrap around within the internal memory area address space and appear to be repeated
1024 times within it.
Write operations might be prevented by programming the Memory Protection Unit of the
product.
Writing of 8-bit and 16-bit data is not allowed and may lead to unpredictable data corruption.
Write operations are performed in the number of wait states equal to the number of wait states
for read operations + 1, except for FWS = 3 (see
The Embedded Flash Controller offers a command set to manage programming the memory
flash, locking and unlocking lock regions, consecutive programming and locking, and full Flash
erasing.
Table 20-1.
In order to perform one of these commands, the Flash Command Register (MC_FCR) has to
be written with the correct command using to the field FCMD (see
ister” on page
Command
Write page
Set Lock Bit
Write Page and Lock
Clear Lock Bit
Erase all
Bytes 0-3
112).
Set of Commands
@2
0-1
3 Wait State Cycles
@4
2-3
Bytes 0-3
Bytes 4-7
@6
4-5
3 Wait State Cycles
@8
6-7
”MC Flash Mode Register” on page
Bytes 8-11
Bytes 4-7
Value
0x01
0x02
0x03
0x04
0x08
@10
8-9 10-11
”MC Flash Command Reg-
Mnemonic
WP
SLB
WPL
CLB
EA
3 Wait State Cycles
@12
Bytes 12-15
6042E–ATARM–14-Dec-06
Bytes 8-11
110).
12-13