AT91SAM7A3-AU Atmel, AT91SAM7A3-AU Datasheet - Page 511
![IC ARM7 MCU FLASH 256K 100LQFP](/photos/6/76/67646/313-100-lqfp_sml.jpg)
AT91SAM7A3-AU
Manufacturer Part Number
AT91SAM7A3-AU
Description
IC ARM7 MCU FLASH 256K 100LQFP
Manufacturer
Atmel
Series
AT91SAMr
Specifications of AT91SAM7A3-AU
Core Processor
ARM7
Core Size
16/32-Bit
Speed
60MHz
Connectivity
CAN, I²C, MMC, SPI, SSC, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
62
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-LQFP
Controller Family/series
AT91SAM7xx
No. Of I/o's
62
Ram Memory Size
32KB
Cpu Speed
60MHz
No. Of Timers
3
Rohs Compliant
Yes
Package
100LQFP
Device Core
ARM7TDMI
Family Name
91S
Maximum Speed
60 MHz
Operating Supply Voltage
3.3 V
Data Bus Width
32 Bit
Number Of Programmable I/os
62
Interface Type
CAN/SPI/I2S/TWI/USART/USB
On-chip Adc
2(8-chx10-bit)
Number Of Timers
3
Processor Series
AT91SAMx
Core
ARM7TDMI
Data Ram Size
32 KB
Maximum Clock Frequency
60 MHz
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
AT91SAM-ICE, AT91-ISP, AT91SAM7A3-EK
Minimum Operating Temperature
- 40 C
Cpu Family
91S
Device Core Size
32b
Frequency (max)
60MHz
Total Internal Ram Size
32KB
# I/os (max)
62
Number Of Timers - General Purpose
3
Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
3V
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
100
Package Type
LQFP
For Use With
AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9AT91SAM7A3-EK - KIT EVAL FOR AT91SAM7A3
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT91SAM7A3-AU
Manufacturer:
MXIC
Quantity:
1 001
Company:
Part Number:
AT91SAM7A3-AU
Manufacturer:
Atmel
Quantity:
730
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Figure 36-12. Receive with Overwrite Mailbox
6042E–ATARM–14-Dec-06
Receive with Overwrite Mailbox
Chaining Mailboxes
(CAN_MSRx)
(CAN_MSRx)
CAN_MDHx)
(CAN_MCRx)
(CAN_MDLx
CAN BUS
MRDY
MTCR
MMI
A mailbox is in Receive with Overwrite Mode once the MOT field in the CAN_MMRx register
has been configured. Message ID and Message Acceptance masks must be set before
Receive Mode is enabled.
After Receive Mode is enabled, the MRDY flag in the CAN_MSR register is automatically
cleared until the first message is received. When the first message has been accepted by the
mailbox, the MRDY flag is set. An interrupt is pending for the mailbox while the MRDY flag is
set. This interrupt is masked depending on the mailbox flag in the CAN_IMR global register.
If a new message is received while the MRDY flag is set, this new message is stored in the
mailbox data register, overwriting the previous message. The MMI flag in the CAN_MSRx reg-
ister notifies the software that a message has been dropped by the mailbox. This flag is
cleared when reading the CAN_MSRx register.
The CAN controller may store a new message in the CAN data registers while the application
reads them. To check that CAN_MDHx and CAN_MDLx do not belong to different messages,
the application must check the MMI field in the CAN_MSRx register before and after reading
CAN_MDHx and CAN_MDLx. If the MMI flag is set again after the data registers have been
read, the software application has to re-read CAN_MDHx and CAN_MDLx (see
Several mailboxes may be used to receive a buffer split into several messages with the same
ID. In this case, the mailbox with the lowest number is serviced first. In the receive and receive
with overwrite modes, the field PRIOR in the CAN_MMRx register has no effect. If Mailbox 0
and Mailbox 5 accept messages with the same ID, the first message is received by Mailbox 0
and the second message is received by Mailbox 5. Mailbox 0 must be configured in Receive
Mode (i.e., the first message received is considered) and Mailbox 5 must be configured in
Receive with Overwrite Mode. Mailbox 0 cannot be configured in Receive with Overwrite
Mode; otherwise, all messages are accepted by this mailbox and Mailbox 5 is never serviced.
Message 1
Reading CAN_MDHx & CAN_MDLx
Reading CAN_MSRx
Message 1
Message 2
Message 2
Message 3
Writing CAN_MCRx
AT91SAM7A3 Preliminary
Message 3
Message 4
Message ID = CAN_MIDx
Message 4
Figure
36-12).
511
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