ATMEGA406-1AAU Atmel, ATMEGA406-1AAU Datasheet - Page 196
ATMEGA406-1AAU
Manufacturer Part Number
ATMEGA406-1AAU
Description
IC AVR MCU 40K 1MHZ 48LQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA406-1AAU
Core Processor
AVR
Core Size
8-Bit
Speed
1MHz
Connectivity
I²C
Peripherals
POR, WDT
Number Of I /o
18
Program Memory Size
40KB (20K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
4 V ~ 25 V
Data Converters
A/D 10x12b
Oscillator Type
Internal
Operating Temperature
-30°C ~ 85°C
Package / Case
48-LQFP
Processor Series
ATMEGA48x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
2 KB
Interface Type
2-Wire
Maximum Clock Frequency
1 MHz
Number Of Programmable I/os
18
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
Minimum Operating Temperature
- 30 C
Cpu Family
ATmega
Device Core
AVR
Device Core Size
8b
Frequency (max)
1MHz
Total Internal Ram Size
2KB
# I/os (max)
18
Number Of Timers - General Purpose
2
Operating Supply Voltage (typ)
5/9/12/15/18/24V
Operating Supply Voltage (max)
25V
Operating Supply Voltage (min)
4V
On-chip Adc
10-chx12-bit
Instruction Set Architecture
RISC
Operating Temp Range
-30C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
48
Package Type
LQFP
Controller Family/series
AVR MEGA
No. Of I/o's
18
Eeprom Memory Size
512Byte
Ram Memory Size
2KB
Cpu Speed
1MHz
Rohs Compliant
Yes
For Use With
770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1005 - ISP 4PORT FOR ATMEL AVR MCU JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPI
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATMEGA406-1AAU
Manufacturer:
AT
Quantity:
20 000
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28.2
28.2.1
196
Fuse Bits
ATmega406
High Byte
Table 28-2.
Notes:
The ATmega406 has two Fuse bytes.
all the fuses and how they are mapped into the Fuse bytes. Note that the fuses are read as logi-
cal zero, “0”, if they are programmed.
Table 28-3.
Notes:
Fuse High Byte
–
–
–
–
–
–
OCDEN
JTAGEN
BLB1
Mode
1
2
3
4
Memory Lock Bits
1. Program the Fuse bits and Boot Lock bits before programming the LB1 and LB2.
2. “1” means unprogrammed, “0” means programmed
1. Never ship a product with the OCDEN Fuse programmed regardless of the setting of Lock bits
(1)
and JTAGEN Fuse. A programmed OCDEN Fuse enables some parts of the clock system to
be running in all sleep modes. This may increase the power consumption.
BLB12
Lock Bit Protection Modes
Fuse High Byte
1
1
0
0
Bit No
BLB11
7
6
5
4
3
2
1
0
1
0
0
1
Description
–
–
–
–
–
–
Enable OCD
Enable JTAG
Protection Type
No restrictions for SPM or LPM accessing the Boot Loader section.
SPM is not allowed to write to the Boot Loader section.
SPM is not allowed to write to the Boot Loader section, and LPM
executing from the Application section is not allowed to read from
the Boot Loader section. If Interrupt Vectors are placed in the
Application section, interrupts are disabled while executing from the
Boot Loader section.
LPM executing from the Application section is not allowed to read
from the Boot Loader section. If Interrupt Vectors are placed in the
Application section, interrupts are disabled while executing from the
Boot Loader section.
Table 28-3
(1)(2)
(Continued)
-
Table 28-4
describe briefly the functionality of
Default Value
1
1
1
1
1
1
1 (unprogrammed, OCD
disabled)
0 (programmed, JTAG enabled)
2548E–AVR–07/06
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