ATMEGA406-1AAU Atmel, ATMEGA406-1AAU Datasheet - Page 189
![IC AVR MCU 40K 1MHZ 48LQFP](/photos/6/76/67647/453-48-lqfp_sml.jpg)
ATMEGA406-1AAU
Manufacturer Part Number
ATMEGA406-1AAU
Description
IC AVR MCU 40K 1MHZ 48LQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA406-1AAU
Core Processor
AVR
Core Size
8-Bit
Speed
1MHz
Connectivity
I²C
Peripherals
POR, WDT
Number Of I /o
18
Program Memory Size
40KB (20K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
4 V ~ 25 V
Data Converters
A/D 10x12b
Oscillator Type
Internal
Operating Temperature
-30°C ~ 85°C
Package / Case
48-LQFP
Processor Series
ATMEGA48x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
2 KB
Interface Type
2-Wire
Maximum Clock Frequency
1 MHz
Number Of Programmable I/os
18
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
Minimum Operating Temperature
- 30 C
Cpu Family
ATmega
Device Core
AVR
Device Core Size
8b
Frequency (max)
1MHz
Total Internal Ram Size
2KB
# I/os (max)
18
Number Of Timers - General Purpose
2
Operating Supply Voltage (typ)
5/9/12/15/18/24V
Operating Supply Voltage (max)
25V
Operating Supply Voltage (min)
4V
On-chip Adc
10-chx12-bit
Instruction Set Architecture
RISC
Operating Temp Range
-30C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
48
Package Type
LQFP
Controller Family/series
AVR MEGA
No. Of I/o's
18
Eeprom Memory Size
512Byte
Ram Memory Size
2KB
Cpu Speed
1MHz
Rohs Compliant
Yes
For Use With
770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1005 - ISP 4PORT FOR ATMEL AVR MCU JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPI
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATMEGA406-1AAU
Manufacturer:
AT
Quantity:
20 000
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- Download datasheet (3Mb)
27.7.10
2548E–AVR–07/06
Reading the Signature Row from Software
To read the Signature Row from software, load the Z-pointer with the signature byte address
given in
is executed within three CPU cycles after the SIGRD and SPMEN bits are set in SPMCSR, the
signature byte value will be loaded in the destination register. The SIGRD and SPMEN bits will
auto-clear upon completion of reading the Signature Row Lock bits or if no LPM instruction is
executed within three CPU cycles. When SIGRD and SPMEN are cleared, LPM will work as
described in the ”AVR Instruction Set” description.
Table 27-5.
Signature Byte
Device ID 0, Manufacture ID
Device ID 1, Flash Size
Device ID 2, Device
FOSCCAL
Reserved
Slow RC FRQ
Slow RC L
Slow RC H
Slow RC Temp Prediction L
Slow RC Temp Prediction H
ULP RC FRQ
ULP RC L
ULP RC H
Bandgap PTAT Current Calibration Byte
V-ADC RAW Cell 1 L
V-ADC RAW Cell 1 H
V-ADC Cell1 Gain Calibration Word L
V-ADC Cell1 Gain Calibration Word H
V-ADC Cell2 Gain Calibration Word L
V-ADC Cell2 Gain Calibration Word H
V-ADC Cell3 Gain Calibration Word L
V-ADC Cell3 Gain Calibration Word H
V-ADC Cell4 Gain Calibration Word L
V-ADC Cell4 Gain Calibration Word H
V-ADC ADC0 Gain Calibration Word L
V-ADC ADC0 Gain Calibration Word H
V-ADC Cell1 Offset
Table 27-5
(1)
(6)
(3)
(5)
(2)
Signature Row Addressing
(12)
and set the SIGRD and SPMEN bits in SPMCSR. When an LPM instruction
(8)
(7)
(9)
(9)
(9)
(9)
(10)
(4)
Z-Pointer Address
0x00
0x02
0x04
0x01
0x03
0x05
0x06
0x07
0x0C
0x0D
0x08
0x0A
0x0B
0x09
0x0E
0x0F
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18
0x19
0x1C
ATmega406
189
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