ATMEGA406-1AAU Atmel, ATMEGA406-1AAU Datasheet - Page 117
ATMEGA406-1AAU
Manufacturer Part Number
ATMEGA406-1AAU
Description
IC AVR MCU 40K 1MHZ 48LQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA406-1AAU
Core Processor
AVR
Core Size
8-Bit
Speed
1MHz
Connectivity
I²C
Peripherals
POR, WDT
Number Of I /o
18
Program Memory Size
40KB (20K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
4 V ~ 25 V
Data Converters
A/D 10x12b
Oscillator Type
Internal
Operating Temperature
-30°C ~ 85°C
Package / Case
48-LQFP
Processor Series
ATMEGA48x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
2 KB
Interface Type
2-Wire
Maximum Clock Frequency
1 MHz
Number Of Programmable I/os
18
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
Minimum Operating Temperature
- 30 C
Cpu Family
ATmega
Device Core
AVR
Device Core Size
8b
Frequency (max)
1MHz
Total Internal Ram Size
2KB
# I/os (max)
18
Number Of Timers - General Purpose
2
Operating Supply Voltage (typ)
5/9/12/15/18/24V
Operating Supply Voltage (max)
25V
Operating Supply Voltage (min)
4V
On-chip Adc
10-chx12-bit
Instruction Set Architecture
RISC
Operating Temp Range
-30C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
48
Package Type
LQFP
Controller Family/series
AVR MEGA
No. Of I/o's
18
Eeprom Memory Size
512Byte
Ram Memory Size
2KB
Cpu Speed
1MHz
Rohs Compliant
Yes
For Use With
770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1005 - ISP 4PORT FOR ATMEL AVR MCU JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPI
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATMEGA406-1AAU
Manufacturer:
AT
Quantity:
20 000
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20.2
2548E–AVR–07/06
Operation
Figure 20-1. Voltage ADC Block Schematic
To enable V-ADC conversions, the V-ADC Enable bit, VADEN, in V-ADC Control and Status
Register – VADCSR must be set. If this bit is cleared, the V-ADC will be switched off, and any
ongoing conversions will be terminated. The V-ADC is automatically halted in Power-save,
Power-down and Power-off mode. Note that the bandgap voltage reference must be enabled
and disabled separately, see “BGCCR – Bandgap Calibration C Register” on page 123.
Figure 20-2. Voltage ADC Conversion Diagram
To perform a V-ADC conversion, the analog input channel must first be selected by writing to the
VADMUX bits in VADMUX. When a logical one is written to the V-ADC Start Conversion bit
VADSC, a conversion of the selected channel will start. The VADSC bit stays high as long as the
conversion is in progress and will be cleared by hardware when the conversion is completed. If a
different data channel is selected while a conversion is in progress, the ADC will finish the cur-
rent conversion before performing the channel change. When a conversion is finished the V-
Conversion Result
Start Conversion
VTEMP
ADC3
ADC2
ADC1
ADC0
ADC4
PV4
PV3
PV2
PV1
NV
Interrupt
Note:
The shaded signals are scaled by 0.2,
other signals are scaled by 1.0
OLD DATA
INPUT
MUX
INVALID DATA
519 us
SIGMA-DELTA ADC
VREF
V-ADC MULTIPLEXER
8-BIT DATA BUS
V-ADC CONTROL
SEL. REG (VADMUX)
12-BIT
SGND
V-ADC CONVERSION COMPLETE IRQ
V A L I D
STATUS REG (VADCSR)
V-ADC DATA REGISTER
V-ADC CONTROL AND
D ATA
(VADCL/ADCH)
ATmega406
INVALID DATA
117
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