ATMEGA406-1AAU Atmel, ATMEGA406-1AAU Datasheet - Page 169
![IC AVR MCU 40K 1MHZ 48LQFP](/photos/6/76/67647/453-48-lqfp_sml.jpg)
ATMEGA406-1AAU
Manufacturer Part Number
ATMEGA406-1AAU
Description
IC AVR MCU 40K 1MHZ 48LQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA406-1AAU
Core Processor
AVR
Core Size
8-Bit
Speed
1MHz
Connectivity
I²C
Peripherals
POR, WDT
Number Of I /o
18
Program Memory Size
40KB (20K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
4 V ~ 25 V
Data Converters
A/D 10x12b
Oscillator Type
Internal
Operating Temperature
-30°C ~ 85°C
Package / Case
48-LQFP
Processor Series
ATMEGA48x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
2 KB
Interface Type
2-Wire
Maximum Clock Frequency
1 MHz
Number Of Programmable I/os
18
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
Minimum Operating Temperature
- 30 C
Cpu Family
ATmega
Device Core
AVR
Device Core Size
8b
Frequency (max)
1MHz
Total Internal Ram Size
2KB
# I/os (max)
18
Number Of Timers - General Purpose
2
Operating Supply Voltage (typ)
5/9/12/15/18/24V
Operating Supply Voltage (max)
25V
Operating Supply Voltage (min)
4V
On-chip Adc
10-chx12-bit
Instruction Set Architecture
RISC
Operating Temp Range
-30C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
48
Package Type
LQFP
Controller Family/series
AVR MEGA
No. Of I/o's
18
Eeprom Memory Size
512Byte
Ram Memory Size
2KB
Cpu Speed
1MHz
Rohs Compliant
Yes
For Use With
770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1005 - ISP 4PORT FOR ATMEL AVR MCU JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPI
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATMEGA406-1AAU
Manufacturer:
AT
Quantity:
20 000
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25.10 Bus Connect/Disconnect for Two-wire Serial Interface
25.10.1
2548E–AVR–07/06
TWBCSR – TWI Bus Control and Status Register
The Bus Connect/Disconnect module is an addition to the TWI Interface. Based on a configura-
tion bit, an interrupt can be generated either when the TWI bus is connected or disconnected.
Figure 25-23
data and clock lines, respectively.
When the TWI bus is connected, both the SDA and the SCL lines will become high simulta-
neously. If the TWBCIP bit is cleared, the interrupt will be executed if enabled. Once the bus is
connected, the TWBCIP bit should be set. This enables detection of when the bus is discon-
nected, and prevents repetitive interrupts every time both the SDA and SCL lines are high (e.g.
bus IDLE state).
When the TWI bus is disconnected, both the SDA and the SCL lines will become low simulta-
neously. If the TWBCIP bit is set, the interrupt will be executed if enabled and if both lines
remain low for a configurable time period. By adding this time constraint, unwanted interrupts
caused by both lines going low during normal bus communication is prevented.
Figure 25-23. Overview of Bus Connect/Disconnect.
• Bit 7 - TWBCIF: TWI Bus Connect/Disconnect Interrupt Flag
Based on the TWBCIP bit, the TWBCIF bit is set when the TWI bus is connected or discon-
nected. TWBCIF is cleared by hardware when executing the corresponding interrupt handling
vector. Alternatively, TWBCIF is cleared by writing a logic one to the flag. When the SREG I-bit,
TWBCIE (TWI Bus Connect/Disconnect Interrupt Enable), and TWBCIF are set, the TWI Bus
Bit
(0xBE)
Read/Write
Initial Value
SDA
SCL
TWBCIF
illustrates the Bus Connect/Disconnect logic, where SDA and SCL are the TWI
R/W
7
X
TWBCIE
R/W
6
0
5
–
R
0
R
4
–
0
TWBCIP
START
R
3
–
0
DELAY ELEMENT
TWBDT1
8-BIT DATA BUS
TWBCSR
R/W
2
0
DELAY
TWBDT0
OUTPUT
R/W
1
0
SET TWBCIF
TWBCIP
R/W
0
0
ATmega406
TWBCSR
IRQ
169
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