ATMEGA406-1AAU Atmel, ATMEGA406-1AAU Datasheet - Page 118
![IC AVR MCU 40K 1MHZ 48LQFP](/photos/6/76/67647/453-48-lqfp_sml.jpg)
ATMEGA406-1AAU
Manufacturer Part Number
ATMEGA406-1AAU
Description
IC AVR MCU 40K 1MHZ 48LQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA406-1AAU
Core Processor
AVR
Core Size
8-Bit
Speed
1MHz
Connectivity
I²C
Peripherals
POR, WDT
Number Of I /o
18
Program Memory Size
40KB (20K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
4 V ~ 25 V
Data Converters
A/D 10x12b
Oscillator Type
Internal
Operating Temperature
-30°C ~ 85°C
Package / Case
48-LQFP
Processor Series
ATMEGA48x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
2 KB
Interface Type
2-Wire
Maximum Clock Frequency
1 MHz
Number Of Programmable I/os
18
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
Minimum Operating Temperature
- 30 C
Cpu Family
ATmega
Device Core
AVR
Device Core Size
8b
Frequency (max)
1MHz
Total Internal Ram Size
2KB
# I/os (max)
18
Number Of Timers - General Purpose
2
Operating Supply Voltage (typ)
5/9/12/15/18/24V
Operating Supply Voltage (max)
25V
Operating Supply Voltage (min)
4V
On-chip Adc
10-chx12-bit
Instruction Set Architecture
RISC
Operating Temp Range
-30C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
48
Package Type
LQFP
Controller Family/series
AVR MEGA
No. Of I/o's
18
Eeprom Memory Size
512Byte
Ram Memory Size
2KB
Cpu Speed
1MHz
Rohs Compliant
Yes
For Use With
770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1005 - ISP 4PORT FOR ATMEL AVR MCU JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPI
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATMEGA406-1AAU
Manufacturer:
AT
Quantity:
20 000
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20.3
20.3.1
20.3.2
118
Register Description
ATmega406
VADMUX – V-ADC Multiplexer Selection Register
VADCSR – V-ADC Control and Status Register
ADC Conversion Complete Interrupt Flag – VADCCIF is set. One 12-bit conversion takes 519 µs
to complete from the start bit is set to the interrupt flag is set. To ensure that correct data is read,
both high and low byte data registers should be read before starting a new conversion.
• Bit 7:4 – RES: Reserved Bits
These bits are reserved bits in the ATmega406 and will always read as zero.
• Bit 3:0 – VADMUX3:0: V-ADC Channel Selection Bits
The VADMUX bits determine the V-ADC channel selection. See
Table 20-1.
• Bit 7:4 – RES: Reserved Bits
These bits are reserved bits in the ATmega406 and will always read as zero.
• Bit 3 – VADEN: V-ADC Enable
Writing this bit to one enables V-ADC conversion. By writing it to zero, the V-ADC is turned off.
Turning the V-ADC off while a conversion is in progress will terminate this conversion. Note that
the bandgap voltage reference must be enabled separately, see “BGCCR – Bandgap Calibra-
tion C Register” on page 123.
Bit
(0x7C)
Read/Write
Initial Value
Bit
(0x7A)
Read/Write
Initial Value
VADMUX3:0
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
VADMUX channel selection
R
7
–
0
R
7
0
–
R
6
–
0
R
6
0
–
R
5
–
0
R
5
0
–
Channel Selected
CELL 1
CELL 2
CELL 3
CELL 4
ADC4
VTEMP
ADC0
ADC1
ADC2
ADC3
R
R
4
–
0
4
–
0
VADMUX3
VADEN
R/W
R/W
3
0
3
0
VADMUX2
VADSC
R/W
R/W
2
0
2
0
Table 20-1 on page
Scale
0.2
0.2
0.2
0.2
0.2
1.0
1.0
1.0
1.0
1.0
VADMUX1
VADCCIF
R/W
R/W
1
0
1
0
VADMUX0
VADCCIE
R/W
R/W
0
0
0
0
2548E–AVR–07/06
118.
VADMUX
VADCSR
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