ADE7566ASTZF8-RL2 AD [Analog Devices], ADE7566ASTZF8-RL2 Datasheet - Page 93

• Manufacturer Part Number: ADE7566ASTZF8-RL2
• Description: Single-Phase Energy Measurement IC with 8052 MCU, RTC, and LCD Driver
• Manufacturer: AD [Analog Devices]

Preliminary Technical Data
A 96 segment LCD with 4× multiplexing requires 96/4 = 24
segment lines. Sixteen pins, FP0 to FP15, are automatically
dedicated for use as LCD segments. Eight more pins must be
chosen for the LCD function. Because the LCD has 4× multi-
plexing, all four common lines are used. As a result, COM2/FP28
and COM3/FP27 cannot be utilized as segment lines. Based on
the alternate functions of the pins used for FP16 through FP25,
FP16 to F23 are chosen for the seven remaining segment lines.
The LCD is setup with the following 8052 code:
; setup LCD pins to have LCD functionality
MOV
MOV
; setup LCDCON for f
MOV
; setup LCDCONX for charge pump and BIASLVL[1110111]
MOV
; set up refresh rate for 64Hz with f
MOV
; set up LCD data registers with data to be displayed using
; LCDPTR and LCDDATA registers
; turn all segments on FP25 ON and FP26 OFF
ORL
MOV
MOV
ANL
ORL
To setup the same 3.3 V LCD for use with an external resistor ladder:
; setup LCD pins to have LCD functionality
MOV
MOV
; setup LCDCON for f
MOV
; setup LCDCONX for external resistor ladder
MOV
; set up refresh rate for 64Hz with f
MOV
; set up LCD data registers with data to be displayed using
; LCDPTR and LCDDATA registers
; turn all segments on FP25 ON and FP26 OFF
ORL
MOV
MOV
ANL
ORL
LCDSEG, # FP20EN+FP21EN+FP22EN+FP23EN
LCDSEGX, #FP16EN+FP17EN+FP18EN+FP19EN
LCDCON, #BIAS+LMUX1+LMUX0
LCDCONX, #BIASLVL5+BIASLVL4+BIASLVL3+ BIASLVL2+BIASLVL1+BIASLVL0
LCDCLK, #FD3+FD2+FD1+FD0
LCDCONY,#01h ; start data memory refresh
LCDDAT, #F0H
LCDCONY,#0FEh ; end of data memory refresh
LCDCON,#LCDEN ; enable LCD
LCDSEG, #FP20EN+FP21EN+FP22EN+FP23EN
LCDSEGX, #FP16EN+FP17EN+FP18EN+FP19EN
LCDCON, #BIAS+LMUX1+LMUX0
LCDCONX, #EXTRES
LCDCLK, #FD3+FD2+FD1+FD0
LCDCONY,#01h ; start data memory refresh
LCDDAT, #F0H
LCDCONY,#0FEh ; end of data memory refresh
LCDCON,#LCDEN ; enable LCD
LCDPTR, #80h OR 0DH
LCDPTR, #80h OR 0DH
LCDCLK
LCDCLK
=2048Hz, 1/3 bias and 4x multiplexing
=2048Hz, 1/3 bias and 4x multiplexing
LCDCLK
LCDCLK
=2048Hz
=2048Hz
Rev. PrA | Page 93 of 136
These pins are enabled for LCD functionality in the LCD
Segment Enable SFR (LCDSEGE, 0x97) and LCD Segment
Enable 2 SFR (LCDSEGE2, 0xED).
To determine contrast setting for this 5 V LCD, Table 76 shows
the BIASLVL[5:0] setting that corresponds to a VC of 5 V in
1/3 bias mode. The nominal bias level setting for this LCD is
BIASLVL[5:0] = [111111].
ADE7566/ADE7569