ADE7566ASTZF8-RL2 AD [Analog Devices], ADE7566ASTZF8-RL2 Datasheet - Page 100

• Manufacturer Part Number: ADE7566ASTZF8-RL2
• Description: Single-Phase Energy Measurement IC with 8052 MCU, RTC, and LCD Driver
• Manufacturer: AD [Analog Devices]

ADE7566/ADE7569
TIMERS
Each ADE7566/ADE7569 has three 16-bit timer/counters: Timer 0,
Timer 1, and Timer 2. The timer/counter hardware is included
on-chip to relieve the processor core of overhead inherent in
implementing timer/counter functionality in software. Each
timer/counter consists of two 8-bit registers: THx and TLx
(x = 0, 1, or 2). All three can be configured to operate either as
timers or as event counters.
When functioning as a timer, the TLx register is incremented
every machine cycle. Thus, users can think of it as counting
machine cycles. Because a machine cycle on a single-cycle core
consists of one core clock period, the maximum count rate is
the core clock frequency.
Table 98. Timer SFRs
SFR
TCON
TMOD
TL0
TL1
TH0
TH1
T2CON
RCAP2L
RCAP2H
TL2
TH2
TIMER SFR REGISTERS
Table 99. Timer/Counter 0 and Timer/Counter 1 Mode SFR (TMOD, 0x89)
Bit No.
7
6
5 to 4
3
2
1 to 0
Mnemonic
Gate1
C/T1
T1/M1,
T1/M0
Gate0
C/T0
T0/M1,
T0/M0
Address
0x89
0x8A
0x8B
0x8C
0x8D
0xC8
0xCA
0xCB
0xCC
0xCD
0x88
Default
0
0
00
0
0
00
Bit Addressable
Yes
No
No
No
No
No
Yes
No
No
No
No
Description
Timer 1 Gating Control. Set by software to enable Timer/Counter 1 only when the INT1 pin is high and
the TR1 control is set. Cleared by software to enable Timer 1 whenever the TR1control bit is set.
Timer 1 Timer or Counter Select Bit. Set by software to select counter operation (input from T1 pin).
Cleared by software to select the timer operation (input from internal system clock).
Timer 1 Mode Select Bits.
T1/M[1:0]
00
01
10
11
Timer 0 Gating Control. Set by software to enable Timer/Counter 0 only when the INT0 pin is high and the
TR0 control bit is set. Cleared by software to enable Timer 0 whenever the TR0 control bit is set.
Timer 0 Timer or Counter Select Bit. Set by software to the select counter operation (input from T0 pin).
Cleared by software to the select timer operation (input from internal system clock).
Timer 0 Mode Select Bits.
T0/M[1:0]
00
01
10
11
Result
TH1 operates as an 8-bit timer/counter. TL1 serves as 5-bit prescaler.
16-Bit Timer/Counter. TH1 and TL1 are cascaded; there is no prescaler.
8-Bit Autoreload Timer/Counter. TH1 holds a value that is to be reloaded into TL1 each
time it overflows.
Timer/Counter 1 Stopped.
Result
TH0 operates as an 8-bit timer/counter. TL0 serves as a 5-bit prescaler.
16-Bit Timer/Counter. TH0 and TL0 are cascaded; there is no prescaler.
8-Bit Autoreload Timer/Counter. TH0 holds a value that is to be reloaded into TL0 each
time it overflows.
TL0 is an 8-bit timer/counter controlled by the standard Timer 0 control bits. TH0 is an
8-bit timer only, controlled by Timer 1 control bits.
Rev. PrA | Page 100 of 136
Timer0 and Timer1 Control Register (see Table 100).
Timer0 and Timer1 Mode Register (see Table 99).
Timer0 LSB (see Table 103).
Timer1 LSB (see Table 105).
Timer0 MSB (see Table 102).
Timer1 MSB (see Table 104).
Timer2 Control Register (see Table 101).
Timer2 Reload/Capture LSB (see Table 109).
Timer2 Reload/Capture MSB (see Table 108).
Timer2 LSB (see Table 107).
Timer2 MSB (see Table 106).
Description
When functioning as a counter, the TLx register is incremented
by a 1-to-0 transition at its corresponding external input pin:
T0, T1, or T2. When the samples show a high in one cycle and a
low in the next cycle, the count is incremented. Because it takes
two machine cycles (two core clock periods) to recognize a 1-to-0
transition, the maximum count rate is half the core clock frequency.
There are no restrictions on the duty cycle of the external input
signal, but to ensure that a given level is sampled at least once
before it changes, it must be held for a minimum of one full
machine cycle. User configuration and control of all timer
operating modes is achieved via the SFRs in Table 98.
Preliminary Technical Data