ADE7566ASTZF8-RL2 AD [Analog Devices], ADE7566ASTZF8-RL2 Datasheet - Page 105

• Manufacturer Part Number: ADE7566ASTZF8-RL2
• Description: Single-Phase Energy Measurement IC with 8052 MCU, RTC, and LCD Driver
• Manufacturer: AD [Analog Devices]

Preliminary Technical Data
PLL
The ADE7566/ADE7569 are intended for use with a 32.768 kHz
watch crystal. A PLL locks onto a multiple of this frequency to
provide a stable 4.096 MHz clock for the system. The core can
operate at this frequency or at binary submultiples of it to allow
power savings when maximum core performance is not required.
The default core clock is the PLL clock divided by 4 or 1.024
MHz. The ADE energy measurement clock is derived from the
PLL clock and is maintained at 4.096 MHz/5 MHz, 819.2 kHz
across all CD settings.
PLL SFR REGISTER LIST
Table 111. Power Control SFR (POWCON, 0xC5)
Bit No.
7
6
5
4
3
2 to 0
Table 112. Key SFR (KYREG, 0xC1)
Bit No.
7 to 0
Table 113. Peripheral Configuration SFR (PERIPH, 0xF4)
Bit No.
7
6
5
4
3
2
1 to 0
Mnemonic
Reserved
METER_OFF
Reserved
COREOFF
Reserved
CD[2:0]
Mnemonic
KYREG
Mnemonic
RXFLAG
VSWSOURCE
VDD_OK
PLL_FLT
Reserved
EXTREFEN
RXPROG[1:0]
Default
0
0
0
0
010
Default
0
Default
0
1
0
0
0
00
Description
Reserved.
Set this bit to turn off the modulators and energy metering DSP circuitry to reduce power if metering
functions are not needed in PSM0
Reserved.
Set this bit to shut down the core if in the PSM1 operating mode.
Reserved.
Controls the core clock frequency (f
CD[2:0]
000
001
010
011
100
101
110
111
Description
Write 0xA7 to the KYREG SFR before writing to the POWCON SFR to unlock it.
Write 0xEA to the KYREG SFR before writing to the HTHSEC, SEC, MIN, or HOUR
timekeeping registers to unlock it.
Description
If set, indicates that a Rx edge event triggered wake-up from PSM2.
Indicates the power supply that is connected internally to V
V
If set, indicates that V
If set, indicates that PLL is not locked.
Reserved.
Set this bit if an external reference is connected to the REF
Controls the function of the P1.0/RxD pin.
RXPROG [1:0]
00
01
11
SW
= V
Result (f
4.096
2.048
1.024
0.512
0.256
0.128
0.064
0.032
BAT
.
Rev. PrA | Page 105 of 136
CORE
in MHz)
Result
GPIO
Rx with wake-up disabled
Rx with wake-up enabled
DD
power supply is ok for operation.
CORE
The PLL is controlled by the CD[2:0] bits in the Power Control
SFR (POWCON, 0xC5). To protect erroneous changes to the
Power Control SFR (POWCON, 0xC5), a key is required to
modify the register. First, the Key SFR (KYREG, 0xC1) is
written with the key, 0xA7, and then a new value is written to
the Power Control SFR (POWCON, 0xC5).
If the PLL loses lock, the MCU is reset and the PLL_FLT bit is
set in the Peripheral Configuration SFR (PERIPH, 0xF4). Set
the PLLACK bit in the Start ADC Measurement SFR (ADCGO,
0xD8) to acknowledge the PLL fault, clearing the PLL_FLT bit.
). f
CORE
= 4.096 MHz/2
CD
IN
SW
pin.
ADE7566/ADE7569
. If set, V
SW
= V
DD
. If cleared,