ADE7566ASTZF8-RL2 AD [Analog Devices], ADE7566ASTZF8-RL2 Datasheet - Page 39

• Manufacturer Part Number: ADE7566ASTZF8-RL2
• Description: Single-Phase Energy Measurement IC with 8052 MCU, RTC, and LCD Driver
• Manufacturer: AD [Analog Devices]

Preliminary Technical Data
Table 34. ACCMODE Register (0x0F)
Bit No.
7 to 6
5
4
3
2
1
0
1
Table 35. GAIN Register (0x1B)
Bit No.
7 to 5
4
3
2 to 0
Table 36. Interrupt Status Register 1 SFR (MIRQSTL, 0xDC)
Bit No.
7
6-5
4
3
2
1
0
1
This function is not available in the ADE7566 part.
This function is not available in the ADE7566 part.
Mnemonic
Reserved
VARSIGN
APSIGN
ABSVARM
SAVARM
POAM
ABSAM
Interrupt Flag
ADEIRQFLAG
Reserved
VARSIGN
APSIGN
VANOLOAD
RNOLOAD
APNOLOAD
Mnemonic
PGA2[2:0]
Reserved
CFSIGN_OPT
PGA1[2:0]
1
1
1
1
1
Default
0
0
0
0
0
0
0
Description
This bit is set if any of the ADE status flags that are enabled to generate an ADE interrupt are set. This bit is
automatically cleared when all of the enabled ADE status flags are cleared.
Reserved.
Logic 1 indicates that the reactive power sign has changed according to the configuration of ACCMODE register.
Logic 1 indicates that the active power sign has changed according to the configuration of ACCMODE register.
Logic 1 indicates that an interrupt has been caused by apparent power no-load detected. This interrupt is also
used to reflect the part entering the I
Logic 1 indicates that an interrupt has been caused by reactive power no-load detected.
Logic 1 indicates that an interrupt has been caused by active power no-load detected.
Description
Reserved.
Configuration bit to select event that triggers a reactive power sign interrupt. If set to 0, VARSIGN
interrupt occurs when reactive power changes from positive to negative. If set to 1, VARSIGN interrupt
occurs when reactive power changes from negative to positive.
Configuration bit to select event that triggers an active power sign interrupt. If set to 0, APSIGN interrupt
occurs when active power changes from positive to negative. If set to 1, APSIGN interrupt occurs when
active power changes from negative to positive.
Logic 1 enables absolute value accumulation of reactive power in energy register and pulse output.
Logic 1 enables reactive power accumulation depending on the sign of the active power. If active power
is positive, VAR is accumulated as it is. If active power is negative, the sign of the VAR is reversed for the
accumulation. This accumulation mode affects both the VAR registers (VARHR, RVARHR, LVARHR) and the
pulse output when connected to VAR.
Logic 1 enables positive only accumulation of active power in energy register and pulse output.
Logic 1 enables absolute value accumulation of active power in energy register and pulse output.
Default
000
0
0
000
These bits define the voltage channel input gain.
These bits define the current channel input gain.
Description
PGA2[2:0]
000
001
010
011
100
Reserved.
This bit defines where the CF change of sign detection (APSIGN or VARSIGN) is
implemented.
CFSIGN_OPT
0
1
PGA1[2:0]
000
001
010
011
100
Rev. PrA | Page 39 of 136
rms
no load mode.
1
Result
Gain = 1
Gain = 2
Gain = 4
Gain = 8
Gain = 16
Result
Filtered power signal
On a per CF pulse basis
Result
Gain = 1
Gain = 2
Gain = 4
Gain = 8
Gain = 16
ADE7566/ADE7569