ADE7566ASTZF8-RL2 AD [Analog Devices], ADE7566ASTZF8-RL2 Datasheet - Page 28

• Manufacturer Part Number: ADE7566ASTZF8-RL2
• Description: Single-Phase Energy Measurement IC with 8052 MCU, RTC, and LCD Driver
• Manufacturer: AD [Analog Devices]

ADE7566/ADE7569
Battery Switchover and Power Supply Restored
PSM Interrupt
The ADE7566/ADE7569 can be configured to generate a PSM
interrupt when the source of V
indicating battery switchover. Setting the EBSO bit in the Power
Management Interrupt Enable SFR (IPSME, 0xEC) enables this
event to generate a PSM interrupt.
The ADE7566/ADE7569 can also be configured to generate an
interrupt when the source of V
indicating that the V
the EPSR bit in the Power Management Interrupt Enable SFR
(IPSME, 0xEC) enables this event to generate a PSM interrupt.
The flags in the Power Management Interrupt Flag SFR (IPSMF,
0xF8) for these interrupts, FBSO and FPSR, are set regardless of
whether the respective enable bits have been set. The battery
switchover and power supply restore event flags, FBSO and FPSR,
are latched. These events must be cleared by writing a 0 to these
bits. Bit 6 in the Peripheral Configuration SFR (PERIPH, 0xF4),
VSWSOURCE, tracks the source of V
is connected to V
V
The ADE7566/ADE7569 can be configured to generate a PSM
interrupt when V
configurable threshold. This threshold is set in the Temperature
and Supply Delta SFR (DIFFPROG, 0xF3). See the External
Voltage Measurement section for more information. Setting the
EVDCIN bit in the Power Management Interrupt Enable SFR
(IPSME, 0xEC) enables this event to generate a PSM interrupt.
The V
measurements take place in the background at intervals to
check the change in V
writing to the Start ADC Measurement SFR (ADCGO, 0xD8).
The FVDCIN flag indicates when a V
DCIN
ADC PSM Interrupt
DCIN
voltage is measured using a dedicated ADC. These
DD
DCIN
and cleared when V
DD
changes magnitude by more than a
DCIN
power supply has been restored. Setting
. Conversions can also be initiated by
SW
SW
changes from V
changes from V
SW
DCIN
. The bit is set when V
SW
measurement is ready.
is connected to V
DD
BAT
to V
to V
BAT
DD
Rev. PrA | Page 28 of 136
,
,
BAT
SW
.
See the External Voltage Measurement section for details on
how V
V
The V
measurements take place in the background at intervals to
check the change in V
level is lower than the threshold set in the Battery Detection
Threshold SFR (BATVTH, 0xFA) or when a new measurement
is ready in the Battery ADC Value SFR (BATADC, 0xDF). See
the Battery Measurement section for more information. Setting
the EBAT bit in the Power Management Interrupt Enable SFR
(IPSME, 0xEC) enables this event to generate a PSM interrupt.
V
The V
bit in the Power Management Interrupt Flag SFR (IPSMF, 0xF8)
is set when the V
EVDCIN bit in the Power Management Interrupt Enable SFR
(IPSME, 0xEC) enables this event to generate a PSM interrupt.
This event, which is associated with the SAG monitoring, can
be used to detect a power supply (V
to trigger further actions prior to deciding a switch of V
SAG Monitor PSM Interrupt
The ADE7566/ADE7569 energy measurement DSP monitors
the ac voltage input at the V
register is used to set the threshold for a line voltage SAG event.
The FSAG bit in the Power Management Interrupt Flag SFR
(IPSMF, 0xF8) is set if the line voltage stays below the level set
in the SAGLVL register for the number of line cycles set in the
SAGCYC register. See the Line Voltage Sag Detection section
for more information. Setting the ESAG bit in the Power
Management Interrupt Enable SFR (IPSME, 0xEC) enables this
event to generate a PSM interrupt.
BAT
DCIN
Monitor PSM Interrupt
Monitor PSM Interrupt
BAT
DCIN
DCIN
voltage is measured using a dedicated ADC. These
voltage is monitored by a comparator. The FVDCIN
is measured.
DCIN
Preliminary Technical Data
input level is lower than 1.2 V. Setting the
BAT
. The FBAT bit is set when the battery
P
and V
N
DD
input pins. The SAGLVL
) being compromised and
DD
to V
BAT
.