ADE7566ASTZF8-RL2 AD [Analog Devices], ADE7566ASTZF8-RL2 Datasheet - Page 123

• Manufacturer Part Number: ADE7566ASTZF8-RL2
• Description: Single-Phase Energy Measurement IC with 8052 MCU, RTC, and LCD Driver
• Manufacturer: AD [Analog Devices]

Preliminary Technical Data
SS (Slave Select Pin)
In SPI slave mode, a transfer is initiated by the assertion of SS
low. The SPI port then transmits and receives 8-bit data until
the data is concluded by the deassertion of SS . In slave mode, SS
is always an input.
In SPI master mode, the SS can be used to control data transfer
to a slave device. In the automatic slave select control mode, the
SS is asserted low to select the slave device and then raised to
deselect the slave device after the transfer is complete. Automatic
slave select control is enabled by setting the AUTO_SS bit in the
SPI Configuration Register SFR (SPIMOD1, 0xE8).
In a multimaster system, the SS can be configured as an input so
that the SPI peripheral can operate as a slave in some situations
and as a master in others. In this case, the slave selects for the
slaves controlled by this SPI peripheral should be generated
with general I/O pins.
SPI MASTER OPERATING MODES
The double buffered receive and transmit registers can be used to
maximize the throughput of the SPI peripheral by continuously
streaming out data in master mode. The continuous transmit mode
is designed to use the full capacity of the SPI. In this mode, the
master transmits and receives data until the SPI/I
Buffer SFR (SPI2CTx, 0x9A) is empty at the start of a byte
transfer. Continuous mode is enabled by setting the SPICONT bit
in the SPI Configuration Register SFR (SPIMOD2, 0xE9).The
SPI peripheral also offers a single byte read and a single byte
write function.
In master mode, the type of transfer is handled automatically,
depending on the configuration of the TIMODE and SPICONT
bits in the SPI Configuration Register SFR (SPIMOD2, 0xE9).
Table 139 shows the sequence of events that should be performed
for each master operating mode. Based on the SS configuration,
some of these events take place automatically.
Figure 95 shows the SPI output for certain automatic chip select
and continuous mode selections. Note that if the continuous
mode is not used, a short delay is inserted between transfers.
Table 139. Procedures for Using SPI as a Master
Mode
Single Byte Write
Continuous
SPIMOD2[7] =
SPICONT Bit
0
1
Description of Operation
Step 1.
Step 2.
Step 3.
Step 4.
Step 5.
Step 1.
Step 2.
Step 3.
Step 4.
Step 5.
Step 6.
Write to SPI2CTx SFR.
SS is asserted low and a write routine is initiated.
SPITxIRQ interrupt flag is set when SPI2CTx register is empty.
SS is deasserted high.
Write to SPI2CTx SFR to clear SPITxIRQ interrupt flag.
Write to SPI2CTx SFR.
SS is asserted low and write routine is initiated.
Wait for SPITxIRQ interrupt flag to write to SPI2CTx SFR.
Transfer continues until the SPI2CTx register and transmit shift registers are empty.
SPITxIRQ interrupt flag is set when SPI2CTx register is empty.
SS is deasserted high.
Write to SPI2CTx SFR to clear SPITxIRQ interrupt flag.
2
C Transmit
Rev. PrA | Page 123 of 136
Note that reading the content of the SPI/I
(SPI2CRx, 0x9B) should be done using a 2-cycle instruction set
such as MOV A or SPI2CRX. Using a 3-cycle instruction such
as MOV 0x3D or SPI2CRX will not transfer the right
information into the target register.
(MANUAL SS CONTROL)
Figure 95. Automatic Chip Select and Continuous Mode Output
AUTO_SS = 1
AUTO_SS = 1
AUTO_SS = 0
SPICONT = 1
SPICONT = 0
SPICONT = 0
DOUT
SCLK
DOUT
DOUT
SCLK
SCLK
DIN
SS
DIN
DIN
SS
SS
DOUT1
DOUT1
DIN1
ADE7566/ADE7569
DIN1
DOUT1
DIN1
2
C Receive Buffer SFR
DOUT2
DIN2
DOUT2
DIN2
DOUT2
DIN2