ADE7566ASTZF8-RL2 AD [Analog Devices], ADE7566ASTZF8-RL2 Datasheet - Page 59

• Manufacturer Part Number: ADE7566ASTZF8-RL2
• Description: Single-Phase Energy Measurement IC with 8052 MCU, RTC, and LCD Driver
• Manufacturer: AD [Analog Devices]

Preliminary Technical Data
VAR Absolute Accumulation Mode
The ADE7569 is placed in absolute accumulation mode by
setting the ABSVARM bit in the ACCMODE Register (0x0F). In
absolute accumulation mode, the reactive energy accumulation
is done by using the absolute reactive power and ignoring any
occurrence of power below the no-load threshold for the active
energy (see Figure 55). The CF pulse also reflects this
accumulation method when in the absolute accumulation mode.
The default setting for this mode is off. Transitions in the direction
of power flow and no-load threshold are active in this mode.
Reactive Energy Pulse Output
The ADE7569 provides all the circuitry with a pulse output
whose frequency is proportional to reactive power (see the
Energy-to-Frequency Conversion section). This pulse
frequency output uses the calibrated signal after VARGAIN,
and its behavior is consistent with the setting of the reactive
energy accumulation mode in the ACCMODE Register (0x0F).
The pulse output is active low and should preferably be connected
to an LED as shown in Figure 66.
Figure 60. Reactive Energy Accumulation in Absolute Accumulation Mode
REACTIVE ENERGY
REACTIVE POWER
THRESHOLD
THRESHOLD
NO-LOAD
NO-LOAD
FROM VOLTAGE
CHANNEL ADC
OUTPUT
FROM
LPF2
VAROS[15:0]
LPF1
VARGAIN[11:0]
ZERO-CROSSING
DETECTION
Figure 61. Line Cycle Reactive Energy Accumulation Mode
DIGITAL-TO-FREQUENCY
CONVERTER
VARDIV[7:0]
TO
%
LINCYC [15:0]
Rev. PrA | Page 59 of 136
CALIBRATION
CONTROL
+
+
Line Cycle Reactive Energy Accumulation Mode
In line cycle reactive energy accumulation mode, the energy
accumulation of the ADE7569 can be synchronized to the
voltage channel zero crossing so that reactive energy can be
accumulated over an integral number of half-line cycles. The
advantage of this mode is similar to the ones described in the
Line Cycle Active Energy Accumulation Mode section.
In line cycle active energy accumulation mode, the ADE7569
accumulates the reactive power signal in the LVARHR register
for an integral number of line cycles, as shown in Figure 61. The
number of half-line cycles is specified in the LINCYC register.
The ADE7569 can accumulate active power for up to 65,535
half-line cycles.
Because the reactive power is integrated on an integral number
of line cycles, the CYCEND flag in the Interrupt Status Register
3 SFR (MIRQSTH, 0xDE) is set at the end of an active energy
accumulation line cycle. If the CYCEND enable bit in the
Interrupt Enable Register 3 SFR (MIRQENH, 0xDB) is set, the
8052 core has a pending ADE interrupt. The ADE interrupt
stays active until the CYCEND status bit is cleared (see the
Energy Measurement Interrupts section). Another calibration
cycle starts as soon as the CYCEND flag is set. If the LVARHR
register is not read before a new CYCEND flag is set, the
LVARHR register is overwritten by a new value.
When a new half-line cycle is written in the LWATTHR register,
the LVARHR register is reset, and a new accumulation starts at
the next zero crossing. The number of half-line cycles is then
counted until LINCYC is reached. This implementation
provides a valid measurement at the first CYCEND interrupt
after writing to the LINCYC register. The line reactive energy
accumulation uses the same signal path as the reactive energy
accumulation. The LSB size of these two registers is equivalent.
48
23
LVARHR [23:0]
0
ACCUMULATE REACTIVE
ENERGY IN INTERNAL
REGISTER AND UPDATE
THE LVARHR REGISTER
AT THE END OF LINCYC
HALF LINE CYCLES
ADE7566/ADE7569
0