ADE7566ASTZF8-RL2 AD [Analog Devices], ADE7566ASTZF8-RL2 Datasheet
ADE7566ASTZF8-RL2
Related parts for ADE7566ASTZF8-RL2
ADE7566ASTZF8-RL2 Summary of contents
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Preliminary Technical Data GENERAL FEATURES Wide supply voltage operation: 2 3.7 V Battery supply input with automatic switchover Reference: 1.2 V ± 1% (drift 50 ppm/°C maximum) 64-lead RoHS package options Lead frame chip scale package (LFCSP) Low ...
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ADE7566/ADE7569 TABLE OF CONTENTS General Features ............................................................................... 1 Energy Measurement Features........................................................ 1 Microprocessor Features.................................................................. 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 4 Specifications..................................................................................... 5 Timing Specifications....................................................................... 9 Absolute Maximum Ratings.......................................................... 16 Thermal Resistance .................................................................... 16 ESD Caution................................................................................ 16 ...
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Preliminary Technical Data LCD Function in PSM2..............................................................92 Flash Memory ..................................................................................94 Overview ......................................................................................94 Flash Memory Organization......................................................95 Using the Flash Memory ............................................................95 Protecting the Flash ....................................................................98 In-Circuit Programming ............................................................99 Timers ............................................................................................ 100 Timer SFR Registers ................................................................ 100 Timer 0 and Timer 1................................................................ ...
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ADE7566/ADE7569 FUNCTIONAL BLOCK DIAGRAM 1.20V REF + PGA1 ADC – MEASUREMENT + ADC PGA2 – DGND 63 54 AGND TEMP TEMP SENSOR ADC BATTERY V ...
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Preliminary Technical Data SPECIFICATIONS V = 3.3 V ± 5%, AGND = DGND = 0 V, on-chip reference XTAL = 32.768 kHz Table 1. Parameter ENERGY METERING MEASUREMENT ACCURACY 1 Phase Error Between Channels PF = 0.8 Capacitive ...
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ADE7566/ADE7569 Parameter POWER-ON RESET (POR) V POR DD Detection Threshold POR Active Timeout Period Strobe Period in Battery Operation V POR SWOUT Detection Threshold POR Active Timeout Period V POR INTD Detection Threshold POR Active Timeout Period V POR INTA ...
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Preliminary Technical Data Parameter DIGITAL INTERFACE LOGIC INPUTS All Inputs Except XTAL1, XTAL2, BCTRL, INT0, INT1, RESET Input High Voltage, V INH Input Low Voltage, V INL BCTRL, INT0, INT1, RESET Input High Voltage, V INH Input Low Voltage, V ...
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ADE7566/ADE7569 Parameter POWER SUPPLY CURRENTS Current in Normal Mode (PSM0) Current in PSM1 Current in PSM2 1 These numbers are not production tested but are guaranteed by design and/or characterization data on production release. 2 See the Terminology section for ...
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Preliminary Technical Data TIMING SPECIFICATIONS AC inputs during testing are driven at V and 0.45 V for Logic 0. Timing measurements are made at V minimum for Logic 1 and V maximum for Logic 0 as shown in IL Figure ...
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ADE7566/ADE7569 2 Table 3. I C-Compatible Interface Timing Parameters (400 kHz) Parameter Description t SCLK low pulse width L t SCLK high pulse width H t Start condition hold time SHD t Data setup time DSU t Data hold time ...
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Preliminary Technical Data Table 4. SPI Master Mode Timing (SPICPHA = 1) Parameters Parameter Description t SCLK low pulse width SL t SCLK high pulse width SH t Data output valid after SCLK Edge DAV t Data input setup time ...
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ADE7566/ADE7569 Table 5. SPI Master Mode Timing (SPICPHA = 0) Parameters Parameter Description t SCLK low pulse width SL t SCLK high pulse width SH t Data output valid after SCLK edge DAV t Data output setup before SCLK edge ...
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Preliminary Technical Data Table 6. SPI Slave Mode Timing (SPICPHA = 1) Parameters Parameter Description SCLK edge SS t SCLK low pulse width SL t SCLK high pulse width SH t Data output valid after SCLK edge ...
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ADE7566/ADE7569 Table 7. SPI Slave Mode Timing (SPICPHA = 0) Parameters Parameter Description SCLK edge SS t SCLK low pulse width SL t SCLK high pulse width SH t Data output valid after SCLK edge DAV t ...
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Preliminary Technical Data Table 8. UART Timing (Shift Register Mode) Parameters Parameter Description t Serial port clock cycle time XLXL t Output data setup to clock QVXH t Input data setup to clock DVXH t Input data hold after clock ...
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ADE7566/ADE7569 ABSOLUTE MAXIMUM RATINGS T = 25°C, unless otherwise noted. A Table 9. Parameter V to DGND DGND BAT V to DGND DCIN Input LCD Voltage to AGND, LCDVA, 1 LCDVB, LCDVC Analog Input Voltage to AGND, ...
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Preliminary Technical Data PIN CONFIGURATION AND FUNCTION DESCRIPTIONS COM3/FP27 COM2/FP28 COM1 COM0 P1.2/FP25 P1.3/T2EX/FP24 P1.4/T2/FP23 P1.5/FP22 P1.6/FP21 P1.7/FP20 P0.1/FP19 P2.0/FP18 P2.1/FP17 P2.2/FP16 LCDVC LCDVP2 Table 11. Pin Function Descriptions Pin No. Mnemonic Description 1 COM3/FP27 Common Output. COM3 is used ...
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ADE7566/ADE7569 Pin No. Mnemonic Description 43 P0.2/CF1/RTCCAL General-Purpose Digital I/O Port 0.2. / Calibration Frequency Logic Output. The CF1 logic output gives instantaneous active, reactive, or apparent power information / RTC Calibration Frequency Logic Output. The RTCCAL logic output gives ...
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Preliminary Technical Data TYPICAL PERFORMANCE CHARACTERISTICS Figure 10. Figure 11. Figure 12. Rev. PrA | Page 19 of 136 ADE7566/ADE7569 Figure 13. Figure 14. Figure 15. ...
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ADE7566/ADE7569 Figure 16. Figure 17. Figure 18. Preliminary Technical Data Rev. PrA | Page 20 of 136 Figure 19. Figure 20. Figure 21. ...
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Preliminary Technical Data TERMINOLOGY Measurement Error The error associated with the energy measurement made by the ADE7566/ADE7569 is defined by the following formula: ⎛ Energy Register ⎜ = Percentage Error ⎜ True ⎝ Phase Error Between Channels The digital integrator ...
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ADE7566/ADE7569 SFR MAPPING Table 12. Mnemonic Address IPSMF 0xF8 STRBPER 0xF9 BATVTH 0xFA SCRATCH1 0xFB SCRATCH2 0xFC SCRATCH3 0xFD SCRATCH4 0xFE INTPR 0xFF B 0xF0 DIFFPROG 0xF3 PERIPH 0xF4 BATPR 0xF5 RTCCOMP 0xF6 TEMPCAL 0xF7 SPIMOD1 0xE8 I2CMOD 0xE8 SPIMOD2 ...
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Preliminary Technical Data POWER MANAGEMENT The ADE7566/ADE7569 have an elaborate power management circuitry that manages the regular power supply to battery switchover and power supply failures. The power management functionalities can be accessed directly through the 8052 SFRs (see Table ...
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ADE7566/ADE7569 Table 15. Power Management Interrupt Flag SFR (IPSMF, 0xF8) Bit No. Address Mnemonic Default 7 0xFF FPSR 0 6 0xFE FPSM 0 5 0xFD FSAG 0 4 0xFC RESERVED 0 3 0xFB FVADC 0 2 0xFA FBAT 0 1 ...
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Preliminary Technical Data Table 19. Scratch Pad 1 SFR (SCRATCH1, 0xFB) Bit No. Mnemonic Default Description SCRATCH1 0 Value can be written/read in this register. This value is maintained in all the power-saving modes. Table 20. Scratch ...
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ADE7566/ADE7569 POWER SUPPLY ARCHITECTURE Each ADE7566/ADE7569 have two power supply inputs and require only a single 3.3 V power supply at V BAT operation. A battery backup, or secondary power supply, with a maximum of 3.6 V ...
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Preliminary Technical Data POWER SUPPLY MONITOR INTERRUPT (PSM) The power supply monitor interrupt (PSM) alerts the 8052 core of power supply events. The PSM interrupt is disabled by default. Setting the EPSM bit in the Interrupt Enable and Priority 2 ...
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ADE7566/ADE7569 Battery Switchover and Power Supply Restored PSM Interrupt The ADE7566/ADE7569 can be configured to generate a PSM interrupt when the source of V changes from V SW indicating battery switchover. Setting the EBSO bit in the Power Management Interrupt ...
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Preliminary Technical Data USING THE POWER SUPPLY FEATURES In an energy meter application, the 3.3 V power supply (V typically generated from the ac line voltage and regulated to 3 voltage regulator IC. The pre-regulated dc voltage, ...
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ADE7566/ADE7569 V – SAG LEVEL TRIP POINT SAGCYC = 1 V DCIN 1. 2.75V Figure 26. Power Supply Management Interrupts and Battery Switchover with V Table 24. Power Supply Event Timing Operating Modes Parameter Time ...
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Preliminary Technical Data OPERATING MODES PSM0 (NORMAL MODE) In PSM0, normal operating mode the analog and digital circuitry powered by V are enabled by default. In normal mode, the default clock frequency established during a ...
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ADE7566/ADE7569 3.3 V PERIPHERALS AND WAKE-UP EVENTS Some of the 3.3 V peripherals are capable of waking the ADE7566/ADE7569 from PSM2. The events that can cause the ADE7566/ADE7569 to wake up from PSM2 are listed in the wake-up events column ...
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Preliminary Technical Data TRANSITIONING BETWEEN OPERATING MODES The operating mode of the ADE7566/ADE7569 is determined by the power supply connected Therefore, changes in SW the power supply such as when V switches from when ...
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ADE7566/ADE7569 ENERGY MEASUREMENT The ADE7566/ADE7569 offer a fixed function, energy measurement, digital processing core that provides all the information needed to measure energy in single-phase energy meters. The part provides two ways to access the energy measurements: direct access through ...
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Preliminary Technical Data Table 28. Energy Measurement SFRs Address R/W Name 0x91 R/W MADDPT 0x92 R/W MDATL 0x93 R/W MDATM 0x94 R/W MDATH 0xD1 R VRMSL 0xD2 R VRMSM 0xD3 R VRMSH 0xD4 R IRMSL 0xD5 R IRMSM 0xD6 R ...
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ADE7566/ADE7569 ENERGY MEASUREMENT REGISTERS Table 29. Energy Measurement Register List Address Length MADDPT[6:0] (Bits) Mnemonic R/W 0x00 Reserved – – 0x01 WATTHR R 24 0x02 RWATTHR R 24 0x03 LWATTHR R 24 0x04 VARHR 0x05 RVARHR ...
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Preliminary Technical Data Address Length MADDPT[6:0] Mnemonic R/W (Bits) 0x27 CF1NUM R/W 16 0x28 CF1DEN R/W 16 0x29 CF2NUM R/W 16 0x2A CF2DEN R This function is not available in the ADE7566 part. ENERGY MEASUREMENT INTERNAL REGISTERS DETAILS ...
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ADE7566/ADE7569 Table 32. WAVMODE Register (0x0D) Bit No. Mnemonic Default WAV2SEL[2:0] 000 WAV1SEL[2:0] 000 DTRT[1: This function is not available in the ADE7566 part. Table 33. NLMODE Register (0x0E) ...
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Preliminary Technical Data Table 34. ACCMODE Register (0x0F) Bit No. Mnemonic Default Description Reserved 0 Reserved VARSIGN 0 Configuration bit to select event that triggers a reactive power sign interrupt. If set to 0, VARSIGN ...
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ADE7566/ADE7569 Table 37. Interrupt Status Register 2 SFR (MIRQSTM, 0xDD) Bit No. Interrupt Flag Description 7 CF2 Logic 1 indicates that a pulse on CF2 has been issued. The flag is set even if CF2 pulse output is not enabled ...
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Preliminary Technical Data Table 41. Interrupt Enable Register 3 SFR (MIRQENH, 0xDB) Bit No. Interrupt Enable Bit Description – Reserved 5 WFSM When this bit is set, the WFSM flag set creates a pending ADE interrupt to ...
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ADE7566/ADE7569 ANALOG-TO-DIGITAL CONVERSION Each ADE7566/ADE7569 has two Σ-Δ analog-to-digital converters (ADCs). The outputs of these ADCs are mapped directly to waveform sampling SFRs (Address 0xE2 to Address 0xE7) and are used for energy measurement internal digital signal processing. In PSM1 ...
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Preliminary Technical Data Anti-Aliasing Filter Figure 33 also shows an analog low-pass filter (RC) on the input to the modulator. This filter is present to prevent aliasing, an artifact of all sampled systems. Aliasing means that frequency components in the ...
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ADE7566/ADE7569 ×1, ×2, ×4, ×8, ×16 {GAIN[7:5 PGA2 0.5V, 0.25V, 0.125V, 62.5mV, 31.3mV 0V ANALOG INPUT RANGE *WHEN DIGITAL INTEGRATOR IS ENABLED, FULL-SCALE OUTPUT DATA IS ATTENUATED DEPENDING ON THE SIGNAL FREQUENCY BECAUSE THE ...
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Preliminary Technical Data The ADE7569 has a built-in digital integrator to recover the current signal from the di/dt sensor. The digital integrator on the current channel is switched off by default when the ADE7569 is powered up. Setting INTE bit ...
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ADE7566/ADE7569 POWER QUALITY MEASUREMENTS Zero-Crossing Detection Each ADE7566/ADE7569 has a zero-crossing detection circuit on the voltage channel. This zero crossing is used to produce an external zero-crossing signal (ZX) and is used in calibration mode. The zero-crossing is generated by ...
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Preliminary Technical Data Line Voltage Sag Detection In addition to the detection of the loss of the line voltage signal (zero crossing), the ADE7566/ADE7569 can also be programmed to detect when the absolute value of the line voltage drops below ...
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ADE7566/ADE7569 PHASE COMPENSATION The ADE7566/ADE7569 must work with transducers that can have inherent phase errors. For example, a phase error of 0.1° to 0.3° is not uncommon for a current transformer (CT). These phase errors can vary from part to ...
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Preliminary Technical Data Current Channel RMS Calculation Each ADE7566/ADE7569 simultaneously calculates the rms values for the current and voltage channels in different registers. Figure 48 shows the detail of the signal processing chain for the rms calculation on the current ...
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ADE7566/ADE7569 VOLTAGE CHANNEL Voltage Channel RMS Calculation Figure 49 shows details of the signal processing chain for the rms calculation on the voltage channel. The voltage channel rms value is processed from the samples used in the voltage channel waveform ...
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Preliminary Technical Data Because LPF2 does not have an ideal brick wall, frequency response (see Figure 51), the active power signal has some ripple due to the instantaneous power signal. This ripple is sinusoidal and has a frequency equal to ...
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ADE7566/ADE7569 sgn CURRENT CHANNEL LPF2 VOLTAGE CHANNEL ACTIVE POWER SIGNAL 5 T CLKIN TIME (nT) ACTIVE ENERGY CALCULATION As stated in the Active Power Calculation section, power is defined as the rate of energy flow. This relationship can be expressed ...
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Preliminary Technical Data Figure 53 shows this energy accumulation for full-scale signals (sinusoidal) on the analog inputs. The three displayed curves illustrate the minimum period of time it takes the energy register to roll over when the active power gain ...
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ADE7566/ADE7569 Watt Absolute Accumulation Mode The ADE7566/ADE7569 are placed in watt absolute accumula- tion mode by setting the ABSAM bit in the ACCMODE Register (0x0F). In this mode, the energy accumulation is done using the absolute active power, ignoring any ...
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Preliminary Technical Data When a new half-line cycle is written in the LINCYC register, the LWATTHR register is reset, and a new accumulation starts at the next zero crossing. The number of half-line cycles is then counted until LINCYC is ...
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ADE7566/ADE7569 Reactive Power Gain Calibration Figure 58 shows the signal processing chain for the ADE7569 reactive power calculation. As explained in the Reactive Power Calculation for the ADE7569 section, the reactive power is calculated by applying a low-pass filter to ...
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Preliminary Technical Data When SAVARM in the ACCMODE Register (0x0F) is set, the reactive power is accumulated depending on the sign of the active power. When active power is positive, the reactive power is added the ...
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ADE7566/ADE7569 Integration Time Under Steady Load As mentioned in the Active Energy Calculation, the discrete time sample period (T) for the accumulation register is 1.22 μs (5/CLKIN). With full-scale sinusoidal signals on the analog inputs and the VARGAIN and VARDIV ...
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Preliminary Technical Data VAR Absolute Accumulation Mode The ADE7569 is placed in absolute accumulation mode by setting the ABSVARM bit in the ACCMODE Register (0x0F). In absolute accumulation mode, the reactive energy accumulation is done by using the absolute reactive ...
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ADE7566/ADE7569 APPARENT POWER CALCULATION Apparent power is defined as the maximum power that can be delivered to a load. V and I are the effective voltage and rms rms current delivered to the load, respectively. Therefore, the apparent power (AP) ...
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Preliminary Technical Data APPARENT ENERGY CALCULATION The apparent energy is given as the integral of the apparent power. = ∫ Apparent Energy Apparent Power The ADE7566/ADE7569 achieve the integration of the apparent power signal by continuously accumulating the apparent power ...
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ADE7566/ADE7569 Apparent Energy Pulse Output All the ADE7566/ADE7569 circuitry has a pulse output whose frequency is proportional to apparent power (see the Energy-to- Frequency Conversion section). This pulse frequency output uses the calibrated signal after VAGAIN. This output can also ...
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Preliminary Technical Data ENERGY-TO-FREQUENCY CONVERSION The ADE7566/ADE7569 also provide two energy-to-frequency conversions for calibration purposes. After initial calibration at manufacturing, the manufacturer or end customer often verify the energy meter calibration. One convenient way to do this is for the ...
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ADE7566/ADE7569 ENERGY MEASUREMENT INTERRUPTS The energy measurement part of the ADE7566/ADE7569 has its own interrupt vector for the 8052 core, Vector Address 0x004B (see the Interrupt Vectors section). The bits set in the Interrupt Enable Register 1 SFR (MIRQENL, 0xD9), ...
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Preliminary Technical Data TEMPERATURE, BATTERY, AND SUPPLY VOLTAGE MEASUREMENTS The ADE7566/ADE7569 include temperature measurements as well as battery and supply voltage measurements. These measure- ments enable many forms of compensation. The temperature and supply voltage measurements can be used to ...
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ADE7566/ADE7569 Table 46. Temperature and Supply Delta SFR (DIFFPROG, 0xF3) Bit No. Mnemonic Default Reserved TEMP_DIFF[2: VDCIN_DIFF[2:0] 0 Table 47. Start ADC Measurement SFR (ADCGO, 0xD8) Bit No. Address ...
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Preliminary Technical Data TEMPERATURE MEASUREMENT To provide a digital temperature measurement, each ADE7566/ADE7569 includes a dedicated ADC. An 8-bit Temperature ADC Value SFR (TEMPADC, 0xD7) holds the results of the temperature conversion. The resolution of the temperature measurement is 0.78°C/LSB. ...
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ADE7566/ADE7569 To set up background battery measurements, follow these steps: 1. Configure the Battery Detection Threshold SFR (BATVTH, 0xFA) to establish a low battery threshold. If the BATADC measurement is below this threshold, the FBAT in the Power Management Interrupt ...
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Preliminary Technical Data External Voltage ADC in PSM1 and PSM2 An external voltage conversion is initiated only by certain actions that depend on the operating mode of the ADE7566/ADE7569. • In PSM0 operating mode, the 8052 is active. External voltage ...
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ADE7566/ADE7569 8052 MCU CORE ARCHITECTURE The ADE7566/ADE7569 have an 8052 MCU core and use the 8051 instruction set. Some of the standard 8052 peripherals, such as the UART, have been enhanced. This section describes the standard 8052 core and its ...
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Preliminary Technical Data Table 54. Program Control SFR (PCON, 0x87) Bit No. Default Description 7 0 SMOD bit. Double baud rate control Reserved. Should be left cleared. Table 55. Data Pointer Low SFR (DPL, 0x82) Bits ...
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ADE7566/ADE7569 BASIC 8052 REGISTERS Program Counter (PC) The program counter holds the two byte address of the next instruction to be fetched. The PC is initialized with 0x00 at reset and is incremented after each instruction is performed. Note that ...
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Preliminary Technical Data STANDARD 8052 SFRS The standard 8052 special function registers include the Accumulator, B, PSW, DPTR, and SP SFRs described in the Basic 8052 Registers section. The standard 8052 SFRs also defines timers, the serial port interface, interrupts, ...
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ADE7566/ADE7569 Address 0x80 through Address 0xFF of general-purpose RAM are shared with the special function registers. The mode of addressing determines which memory space is accessed as shown in Figure 70. 0xFF ACCESSIBLE BY ACCESSIBLE BY INDIRECT ADDRESSING DIRECT ADDRESSING ...
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Preliminary Technical Data Direct Addressing With direct addressing, the value at the source address is moved to the destination address. Direct addressing provides the fastest execution time of all the addressing modes when an instruction is performed between registers. Note ...
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ADE7566/ADE7569 INSTRUCTION SET Table 61 documents the number of clock cycles required for each instruction. Most instructions are executed in one or two clock cycles, resulting MIPS peak performance. Table 61. Instruction Set Mnemonic Description ARITHMETIC ADD ...
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Preliminary Technical Data Mnemonic Description RLC A Rotate A Left Through Carry Rotate A Right. RRC A Rotate A Right Through Carry. DATA TRANSFER MOV A,Rn Move Register to A. MOV A,@Ri Move Indirect Memory to A. MOV ...
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ADE7566/ADE7569 Mnemonic Description JNC rel Jump on Carry Equal rel Jump on Accumulator = 0. JNZ rel Jump on Accumulator Not Equal to 0. DJNZ Rn,rel Decrement Register, JNZ Relative. LJMP Long Jump Unconditional. LCALL addr16 Long ...
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Preliminary Technical Data SUBB A, Source This instruction subtracts the source byte and the carry (borrow) flag from the accumulator. It references the carry (borrow) status flag. Affected Status Flags C Set if there is a borrow needed for Bit ...
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ADE7566/ADE7569 INTERRUPT SYSTEM The unique power management architecture of the ADE7566/ADE7569 includes an operating mode (PSM2) where the 8052 MCU core is shut down. Events can be configured to wake the 8052 MCU core from the PSM2 operating mode. A ...
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Preliminary Technical Data Table 65. Interrupt Priority SFR (IP, 0xB8) Bit No. Address Mnemonic 7 0xBF PADE 6 0xBE PTEMP 5 0xBD PT2 4 0xBC PS 3 0xBB PT1 2 0xBA PX1 1 0xB9 PT0 0 0xB8 PX0 Table 66. ...
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ADE7566/ADE7569 INTERRUPT FLAGS The interrupt flags and status flags associated with the interrupt vectors are shown in Table 68 and Table 69. Most of the interrupts have flags associated with them. Table 68. Interrupt Flags Interrupt Source Flags IE0 TCON.1 ...
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Preliminary Technical Data IPSMF FPSM PSM (IPSMF.6) IPSME MIDNIGHT RTC ALARM MIRQSTH MIRQSTM MIRQSTL ADE MIRQENH MIRQENM MIRQENL WATCHDOG TIMEOUT WATCHDOG WDIR TEMPADC INTERRUPT TEMP ADC IT0 0 INT0 EXTERNAL INTERRUPT 0 1 TF0 TIMER 0 IT1 0 EXTERNAL INT1 ...
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ADE7566/ADE7569 INTERRUPT VECTORS When an interrupt occurs, the program counter is pushed onto the stack, and the corresponding interrupt vector address is loaded into the program counter. When the interrupt service routine is complete, the program counter is popped off ...
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Preliminary Technical Data WATCHDOG TIMER The watchdog timer generates a device reset or interrupt within a reasonable amount of time if the ADE7566/ADE7569 enter an erroneous state, possibly due to a programming error or electrical noise. The watchdog is enabled ...
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ADE7566/ADE7569 Writing to the Watchdog Timer SFR (WDCON, 0xC0) Writing data to the WDCON SFR involves a double instruction sequence. The WDWR bit must be set and the following instruction must be a write instruction to the WDCON SFR. Disable ...
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Preliminary Technical Data LCD DRIVER Using shared pins, the LCD module is capable of directly driving an LCD panel of 17 × 4 segments without comprising any ADE7566/ADE7569 functions capable of driving LCDs with 2×, 3×, and 4× ...
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ADE7566/ADE7569 Table 75. LCD Configuration X SFR (LCDCONX, 0x9C) Bit No. Mnemonic Default 7 Reserved 0 6 EXTRES BIASLVL[5:0] 0 Table 76. LCD Bias Voltage When Contrast Control Is Enabled BIASLVL[ ...
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Preliminary Technical Data Table 79. LCD Frame Rate Selection for f FD3 FD2 FD1 FD0 f (Hz) LCD 256 170 128 102 ...
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ADE7566/ADE7569 Table 82. LCD Pointer SFR (LCDPTR, 0xAC) Bit No. Mnemonic Default Description 7 W/R 0 Read or Write LCD Bit. If this bit is set (1), the data in LCDDAT is written to the address indicated by the LCDPTR[5:0] ...
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Preliminary Technical Data BLINK MODE Blink mode is enabled by setting the BLINKEN bit in the LCD Configuration SFR (LCDCON, 0x95). This mode is used to alternate between the LCD on state and LCD off state so that the LCD ...
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ADE7566/ADE7569 VOLTAGE GENERATION The ADE7566/ADE7569 provide two ways to generate the LCD waveform voltage levels. The on-chip charge pump option can generate 5 V. This makes it possible to use 5 V LCDs with the 3.3 V ADE7566/ADE7569. There is ...
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Preliminary Technical Data A 96 segment LCD with 4× multiplexing requires 96 segment lines. Sixteen pins, FP0 to FP15, are automatically dedicated for use as LCD segments. Eight more pins must be chosen for the LCD function. Because ...
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ADE7566/ADE7569 FLASH MEMORY OVERVIEW Flash memory is a type of nonvolatile memory that is in-circuit programmable. The default state of a byte of flash memory is 0xFF (erased). When a byte of flash memory is programmed, the required bits change ...
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Preliminary Technical Data FLASH MEMORY ORGANIZATION The flash memory provided by the ADE7566/ADE7569 are segmented into 32 pages of 512 bytes each the user to decide which flash memory to allocate for data ...
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ADE7566/ADE7569 The program counter (PC) is held on the instruction where the ECON register is written to until the flash memory controller is done performing the requested operation. Then, the PC increments to continue with the next instruction. Table 88. ...
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Preliminary Technical Data Table 94. Flash Read Protection SFR (PROTR, 0xBF) Bit No. Mnemonic Default Description PROTR 0xFF This SFR is used to write the read protection bits for Page 0 to Page 31 of the flash ...
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ADE7566/ADE7569 PROTECTING THE FLASH Two forms of protection are offered for this flash memory: read protection and write/erase protection. The read protection ensures that any pages that are read protected are not able to be read by the end user. ...
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Preliminary Technical Data Enabling Flash Protection by Emulator Commands Another way to set the flash protection bytes is to use some reserved emulator commands available only in download mode. These commands write directly to the SFRs and can be used ...
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ADE7566/ADE7569 TIMERS Each ADE7566/ADE7569 has three 16-bit timer/counters: Timer 0, Timer 1, and Timer 2. The timer/counter hardware is included on-chip to relieve the processor core of overhead inherent in implementing timer/counter functionality in software. Each timer/counter consists of two ...
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Preliminary Technical Data Table 100. Timer/Counter 0 and Timer/Counter 1 Control SFR (TCON, 0x88) Bit No. Address Mnemonic Default 7 0x8F TF1 0 6 0x8E TR1 0 5 0x8D TF0 0 4 0x8C TR0 0x8B IE1 0 ...
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ADE7566/ADE7569 Table 102. Timer 0 High Byte SFR (TH0, 0x8C) Bit No. Mnemonic Default Description TH0 0 Timer 0 Data High Byte. Table 103. Timer 0 Low Byte SFR (TL0, 0x8A) Bit No. Mnemonic Default Description 7 ...
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Preliminary Technical Data Mode 2 (8-Bit Timer/Counter with Autoreload) Mode 2 configures the timer register as an 8-bit counter (TL0) with automatic reload as shown in Figure 84. Overflow from TL0 not only sets TF0, but also reloads TL0 with ...
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ADE7566/ADE7569 f CORE P1.4/T2 TRANSITION DETECTOR P1.3/ T2EX f CORE P1.4/T2 TRANSITION DETECTOR P1.3/ T2EX TL2 TH2 (8 BITS) (8 BITS CONTROL TR2 RELOAD RCAP2L RCAP2H CONTROL EXEN2 Figure 86. Timer/Counter 2, ...
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Preliminary Technical Data PLL The ADE7566/ADE7569 are intended for use with a 32.768 kHz watch crystal. A PLL locks onto a multiple of this frequency to provide a stable 4.096 MHz clock for the system. The core can operate at ...
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ADE7566/ADE7569 Table 114. Start ADC Measurement SFR (ADCGO, 0xD8) Bit No. Address Mnemonic 7 0xDF PLL_FTL_ACK 0xDE to 0xDB Reserved 2 0xDA VDCIN_ADC_GO 1 0xD9 TEMP_ADC_GO 0 0xD8 BATT_ADC_GO Default Description 0 Set this bit to clear ...
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Preliminary Technical Data REAL TIME CLOCK The ADE7566/ADE7569 have an embedded real time clock (RTC) as shown in Figure 88. The external 32.768 kHz crystal is used as the clock source for the RTC. Calibration is provided to compensate the ...
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ADE7566/ADE7569 Table 116. RTC Configuration SFR (TIMECON, 0xA1) Bit No. Mnemonic Default Description 7 MIDNIGHT 0 Midnight Flag. This bit is set when the RTC rolls over to 00:00:00:00. It can be cleared by the user to indicate that the ...
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Preliminary Technical Data Table 121. Alarm Interval SFR (INTVAL, 0xA6) Bit No. Mnemonic Default Description INTVAL 0 The interval timer counts according to the time base established in the ITS[1:0] bits of the RTC Configuration SFR (TIMECON, ...
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ADE7566/ADE7569 READ AND WRITE OPERATIONS Writing to the RTC Registers The RTC circuitry runs off a 32.768 kHz clock. The timekeeping registers, Hundredths of a Second Counter SFR (HTHSEC, 0xA2), Seconds Counter SFR (SEC, 0xA3), Minutes Counter SFR (MIN, 0xA4), ...
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Preliminary Technical Data Take care when changing the interval timer time base. The recommended procedure is as follows the Alarm Interval SFR (INTVAL, 0xA6) is going to be modified, write to this register first. Then, wait for one ...
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ADE7566/ADE7569 UART SERIAL INTERFACE The ADE7566/ADE7569 UART can be configured in one of four modes. • Shift register with baud rate fixed at f • 8-bit UART with variable baud rate • 9-bit UART with baud rate fixed at f ...
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Preliminary Technical Data Table 129. Serial Port Buffer SFR (SBUF, 0x99) Bit No. Mnemonic SBUF Table 130. Enhanced Serial Baud Rate Control SFR (SBAUDT, 0x9E) Bit No. Mnemonic Default 7 OWE ...
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ADE7566/ADE7569 Table 132. Common Baud Rates Using UART Timer with a 4.096 MHz PLL Clock Ideal Baud CD 115200 0 115200 1 57600 0 57600 1 38400 0 38400 1 38400 2 19200 0 19200 1 19200 2 19200 3 ...
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Preliminary Technical Data UART OPERATION MODES Mode 0 (Shift Register with Baud Rate Fixed at f Mode 0 is selected when the SM0 and SM1 bits in the Serial Communications Control Register Bit Description SFR (SCON, 0x98) are cleared. In ...
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ADE7566/ADE7569 To transmit, the 8 data bits must be written into the Serial Port Buffer SFR (SBUF, 0x99). The ninth bit must be written to TB8 in the Serial Communications Control Register Bit Description SFR (SCON, 0x98). When transmission is ...
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Preliminary Technical Data Timer 2 is selected as the baud rate generator by setting TCLK and/or RCLK in Timer/Counter 2 Control SFR (T2CON, 0xC8). The baud rates for transmit and receive can be simultaneously different. Setting RCLK and/or TCLK puts ...
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ADE7566/ADE7569 SBAUDF is the fractional divider ratio required to achieve the required baud rate. The appropriate value for SBAUDF can be calculated with the following formula: ⎛ f ⎜ = × CORE SBAUDF 64 ⎜ + × × DIV SBTH ...
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Preliminary Technical Data SERIAL PERIPHERAL INTERFACE (SPI) The ADE7566/ADE7569 integrate a complete hardware serial peripheral interface on-chip. The SPI is full duplex so that 8 bits of data are synchronously transmitted and simultaneously received. This SPI implementation is double buffered, ...
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ADE7566/ADE7569 Table 136. SPI Configuration Register SFR (SPIMOD1, 0xE8) Bit No. Address Mnemonic 0xEF to 0xEE Reserved 5 0xED INTMOD 4 0xEC AUTO_SS 3 0xEB SS_EN 2 0xEA RxOFW 0xE9 to 0xE8 SPIR[1:0] Default ...
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Preliminary Technical Data Table 137. SPI Configuration Register SFR (SPIMOD2, 0xE9) Bit No. Mnemonic Default Description 7 SPICONT 0 Master Mode, SPI Continuous Transfer Mode Enable Bit. SPICONT SPIEN 0 SPI Interface Enable Bit. SPIEN 0 1 ...
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ADE7566/ADE7569 Table 138. SPI Interrupt Status Register SFR (SPISTAT, 0xEA) Bit No. Mnemonic Default Description 7 BUSY 0 SPI Peripheral Busy Flag. BUSY MMERR 0 SPI Multi-Master Error Flag. MMERR SPIRxOF 0 SPI Receive ...
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Preliminary Technical Data SS (Slave Select Pin) In SPI slave mode, a transfer is initiated by the assertion of SS low. The SPI port then transmits and receives 8-bit data until the data is concluded by the deassertion of SS ...
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ADE7566/ADE7569 SPI INTERRUPT AND STATUS FLAGS The SPI interface has several status flags that indicate the status of the double buffered receive and transmit registers. Figure 96 shows when the status and interrupt flags are raised. The transmit interrupt occurs ...
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Preliminary Technical Data COMPATIBLE INTERFACE The ADE7566/ADE7569 support a fully licensed I 2 The I C interface is implemented as a full hardware master. SDATA is the data I/O pin, and SCLK is the serial clock. These ...
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ADE7566/ADE7569 2 Table 142 Slave Address SFR (I2CADR, 0xE9) Bit No. Mnemonic Default Description I2CSLVADR 0 Address of the I 0 I2CR_W 0 Command Bit for Read or Write. When this bit is set to ...
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Preliminary Technical Data RECEIVE AND TRANSMIT FIFOS 2 The I C peripheral has a 4 byte receive FIFO and a 4 byte transmit FIFO. The buffers reduce the overhead associated with 2 using the I C peripheral. ...
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ADE7566/ADE7569 DUAL DATA POINTERS Each ADE7566/ADE7569 incorporates two data pointers. The second data pointer is a shadow data pointer and is selected via the Data Pointer Control SFR SFR (DPCON, 0xA7). DPCON features automatic hardware post-increment and post- decrement, as ...
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Preliminary Technical Data I/O PORTS PARALLEL I/O The ADE7566/ADE7569 use three input/output ports to exchange data with external devices. In addition to performing general-purpose I/O, some are capable of driving an LCD or performing alternate functions for the peripherals available ...
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ADE7566/ADE7569 I/O SFR REGISTER LIST Table 146. Extended Port Configuration SFR (EPCFG, 0x9F) Bit No. Mnemonic 7 MOD38_FP21 6 MOD38_FP22 5 MOD38_FP23 4 MOD38_TxD 3 MOD38_CF1 2 MOD38_SSb 1 MOD38_MISO 0 MOD38_CF2 Table 147. Port 0 Weak Pull-Up Enable SFR ...
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Preliminary Technical Data Table 150. Port 0 SFR (P0, 0x80) Bit No. Address Mnemonic 7 0x87 T1 6 0x86 T0 5 0x85 4 0x84 3 0x83 CF2 2 0x82 CF1 1 0x81 0 0x80 INT1 1 When an alternate function ...
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ADE7566/ADE7569 Table 153. Port 0 Alternate Functions Pin No. Alternate Function P0.0 BCTRL External Battery Control Input INT1 External Interrupt INT1 Wake-up from PSM2 Operating Mode P0.1 FP19 LCD Segment Pin P0.2 CF1 ADE Calibration Frequency Output P0.3 CF2 ADE ...
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Preliminary Technical Data PORT 0 Port 0 is controlled directly through the bit-addressable Port 0 SFR (P0, 0x80). The weak internal pull-ups for Port 0 are configured through the Port 0 Weak Pull-Up Enable SFR (PINMAP0, 0xB2); they are enabled ...
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ADE7566/ADE7569 DETERMINING THE VERSION OF THE ADE7566/ADE7569 Each ADE7566/ADE7569 holds in its internal flash registers a value that defines its version. This value helps to determine if users have the latest version of the part. The ADE7566/ADE756 version corresponding to ...
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Preliminary Technical Data OUTLINE DIMENSIONS 1.45 1.40 1.35 SEATING PLANE VIEW A ROTATED 90° CCW PIN 1 INDICATOR 12° MAX 1.00 0.85 0.80 SEATING PLANE 0.75 0.60 1.60 MAX 0. PIN 1 0.20 0.09 7° 3.5° 16 0° ...
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... ADE7566/ADE7569 ORDERING GUIDE 1 Model Antitaper ADE7566ACPZF8 ADE7566ACPZF8- ADE7566ACPZF16 No 12 ADE7566ACPZF16- ADE7566ASTZF8 No 2 ADE7566ASTZF8- ADE7566ASTZF16 No 2 ADE7566ASTZF16- ADE7569ACPZF16 No 2 ADE7569ACPZF16- ADE7569ASTZF16 No 2 ADE7569ASTZF16-RL No EVAL- ADE7566F16EB EVAL- ADE7569F16EB 1 All models have rms LCD, and RTC. ...