ADE7566ASTZF8-RL2 AD [Analog Devices], ADE7566ASTZF8-RL2 Datasheet - Page 80

• Manufacturer Part Number: ADE7566ASTZF8-RL2
• Description: Single-Phase Energy Measurement IC with 8052 MCU, RTC, and LCD Driver
• Manufacturer: AD [Analog Devices]

ADE7566/ADE7569
INTERRUPT SYSTEM
The unique power management architecture of the
ADE7566/ADE7569 includes an operating mode (PSM2) where
the 8052 MCU core is shut down. Events can be configured to
wake the 8052 MCU core from the PSM2 operating mode. A
distinction is drawn here between events that can trigger the
wake-up of the 8052 MCU core and events that can trigger an
interrupt when the MCU core is active. Events that can wake
the core are referred to as wake-up events, while events that can
interrupt the program flow when the MCU is active are called
interrupts. See the 3.3 V Peripherals and Wake-Up Events
section to learn more about events that can wake the 8052 core
from PSM2.
The ADE7566/ADE7569 provide 12 interrupt sources with
three priority levels. The power management interrupt is alone
at the highest priority level. The other two priority levels are
configurable through the Interrupt Priority SFR (IP, 0xB8) and
Interrupt Enable and Priority 2 SFR (IEIP2, 0xA9).
STANDARD 8051 INTERRUPT ARCHITECTURE
The 8051 standard interrupt architecture includes two tiers of
interrupts, where some interrupts are assigned a high priority
and others are assigned a low priority.
INTERRUPT REGISTERS
The control and configuration of the interrupt system is carried out through four interrupt-related SFRs discussed in this section.
Table 63. Interrupt SFRs
SFR
IE
IP
IEIP2
WDCON
Table 64. Interrupt Enable SFR (IE, 0xA8)
Bit No.
7
6
5
4
3
2
1
0
Address
0xAF
0xAE
0xAD
0xAC
0xAB
0xAA
0xA9
0xA8
Address
0xA8
0xB8
0xA9
0xC0
Figure 73. Standard 8051 Interrupt Priority Levels
HIGH
LOW
Default
0x00
0x00
0xA0
0x10
Mnemonic
EA
ETEMP
ET2
ES
ET1
EX1
ET0
EX0
PRIORITY 1
PRIORITY 0
Bit Addressable
Yes
Yes
No
Yes
Description
Enables all Interrupt Sources. Set by the user. Cleared by the user to disable all interrupt sources.
Enables the Temperature ADC Interrupt. Set by the user.
Enables the Timer 2 Interrupt. Set by the user.
Enables the UART Serial Port Interrupt. Set by the user.
Enables the Timer 1 Interrupt. Set by the user.
Enables the External Interrupt 1 (INT1). Set by the user.
Enables the Timer 0 Interrupt. Set by the user.
Enables External Interrupt 0 (INT0). Set by the user.
Interrupt Enable Register (see Table 64).
Interrupt Priority Register (see Table 65).
Secondary Interrupt Enable Register (see Table 66).
Watchdog Timer Configuration (see Table 71 and the Writing to the Watchdog Timer
SFR (WDCON, 0xC0) section).
Description
Rev. PrA | Page 80 of 136
A Priority 1 interrupt can interrupt the service routine of a
Priority 0 interrupt, and if two interrupts of different priorities
occur at the same time, the Priority 1 interrupt is serviced first.
An interrupt cannot be interrupted by another interrupt of the
same priority level. If two interrupts of the same priority level
occur simultaneously, a polling sequence is observed. See the
Interrupt Priority section.
INTERRUPT ARCHITECTURE
The ADE7566/ADE7569 possess advanced power supply
monitoring features. To ensure a fast response to time critical
power supply issues, such as a loss of line power, the power
supply monitoring interrupt should be able to interrupt any
interrupt service routine. To enable the user to have full use of the
standard 8051 interrupt priority levels, an additional priority
level was added for the power supply management (PSM)
interrupt. The PSM interrupt is the only interrupt at this highest
interrupt priority level.
See the Power Supply Monitor Interrupt (PSM) section for
more information on the PSM interrupt.
Figure 74. Interrupt Architecture
Preliminary Technical Data
HIGH
LOW
PRIORITY 1
PRIORITY 0
PSM