ADE7566ASTZF8-RL2 AD [Analog Devices], ADE7566ASTZF8-RL2 Datasheet - Page 24

• Manufacturer Part Number: ADE7566ASTZF8-RL2
• Description: Single-Phase Energy Measurement IC with 8052 MCU, RTC, and LCD Driver
• Manufacturer: AD [Analog Devices]

ADE7566/ADE7569
Table 15. Power Management Interrupt Flag SFR (IPSMF, 0xF8)
Bit No.
7
6
5
4
3
2
1
0
Table 16. Battery Switchover Configuration SFR (BATPR, 0xF5)
Bit No.
7 to 2
1 to 0
Table 17. Peripheral Configuration SFR (PERIPH, 0xF4)
Bit No.
7
6
5
4
3
2
1 to 0
Table 18. Power Management Interrupt Enable SFR (IPSME, 0xEC)
Bit No.
7
6
5
4
3
2
1
0
Address
0xFF
0xFE
0xFD
0xFC
0xFB
0xFA
0xF9
0xF8
Mnemonic
RXFLAG
VSWSOURCE
VDD_OK
PLL_FLT
REF_BAT_EN
Reserved
RXPROG[1:0]
Interrupt Enable Bit
EPSR
RESERVED
ESAG
RESERVED
EVSW
EBAT
EBSO
EVDCIN
Mnemonic
Reserved
BATPRG[1:0]
Mnemonic
FPSR
FPSM
FSAG
RESERVED
FVADC
FBAT
FBSO
FVDCIN
Default
0
1
1
0
0
0
00
Default
00
00
Default
0
0
0
0
0
0
0
0
Indicates the power supply that is internally connected to V
Description
If set, indicates that an Rx edge event triggered wake-up from PSM2.
If set, indicates that VDD power supply is ready for operation.
If set, indicates that a PLL fault occurred where the PLL lost lock. Set the PLLACK bit in the Start ADC
Measurement SFR (ADCGO, 0xD8) to acknowledge the fault and clear the PLL_FLT bit.
If set, internal voltage reference enabled in PSM2 mode. This bit should be set if LCD is on in PSM2 mode.
This bit should be kept to zero.
Controls the function of the P1.0/RxD pin.
RXPROG[1:0]
00
01
11
Default
0
0
0
0
0
0
0
0
Description
Power Supply Restored Interrupt Flag. Set when the V
This occurs when the source of V
PSM Interrupt Flag. Set when an enabled PSM interrupt condition occurs.
Voltage SAG Interrupt Flag. Set when an ADE energy measurement SAG condition occurs.
This bit must be kept cleared for proper operation.
V
ready.
V
Battery Switchover Interrupt Flag. Set when V
V
Description
These bits must be kept to 0 for proper operation.
Control Bits for Battery Switchover.
BATPRG[1:0]
00
01
1X
DCIN
BAT
DCIN
Monitor Interrupt Flag. Set when V
Monitor Interrupt Flag. Set when V
Monitor Interrupt Flag. Set when V
Description
Enables a PSM interrupt when the power supply restored flag (FPSR) is set.
Reserved.
Enables a PSM interrupt when the voltage SAG flag (FSAG) is set.
This bit must be kept cleared for proper operation.
Enables a PSM interrupt when the V
Enables a PSM interrupt when the V
Enables a PSM interrupt when the V
Enables a PSM interrupt when the battery switchover flag (BSFO) is set.
Result
GPIO
RxD with wake-up disabled
RxD with wake-up enabled
Rev. PrA | Page 24 of 136
Result
Battery switchover enabled on low V
Battery switchover enabled on low V
Battery switchover disabled
SW
changes from V
BAT
DCIN
falls below BATVTH or when V
DCIN
changes by VDCIN_DIFF or when V
SW
BAT
DCIN
falls below 1.2 V.
monitor flag (FVSW) is set.
monitor flag (FBAT) is set.
monitor flag (FVDCIN) is set.
SW
switches from V
Preliminary Technical Data
SW
BAT
(0 V
DD
to V
DD
DD
power supply has been restored.
SW
and low V
DD
= V
.
BAT
DD
, 1 V
to V
DCIN
BAT
SW
BAT.
measurement is ready.
= V
DCIN
DD
).
measurement is