ADE7566ASTZF8-RL2 AD [Analog Devices], ADE7566ASTZF8-RL2 Datasheet - Page 126

• Manufacturer Part Number: ADE7566ASTZF8-RL2
• Description: Single-Phase Energy Measurement IC with 8052 MCU, RTC, and LCD Driver
• Manufacturer: AD [Analog Devices]

ADE7566/ADE7569
Table 142. I
Bit No.
7 to 1
0
Table 143. I
Bit No.
7
6
5
4
3 to 2
1
0
READ AND WRITE OPERATIONS
Figure 98 and Figure 99 depict I
whether a read or write operation is performed on the slave device. During the read operation, the master acknowledges are generated
automatically by the I
the I2CRCT, Bits[4:0] bits have been read from the slave. If the I2CADR register is updated during a transmission, instead of generating a
stop at the end of the read or write operation, the master generates a start condition and continues with the next communication.
Reading the SPI/I
Reading the SPI2CRx SFR should be done with a 2-cycle instruction, such as
Mov a, spi2crx or Mov R0, spi2crx
A 3-cycle instruction such as
Mov 3dh, spi2crx
will not transfer the right data into RAM Address 0x3d.
SDATA
SCLK
START BY
MASTER
Mnemonic
I2CSLVADR
I2CR_W
Mnemonic
I2CBUSY
I2CNOACK
I2CRxIRQ
I2CTxIRQ
I2CFIFOSTAT[1:0]
I2CACC_ERR
I2CTxWR_ERR
A6
2
2
1
C Slave Address SFR (I2CADR, 0xE9)
C Interrupt Status Register SFR (SPI2CSTAT, 0xEA)
SERIAL BUS ADDRESS BYTE
A5
SDATA
2
SCLK
C Receive Buffer SFR (SPI2CRx, 0x9B)
A4
2
C peripheral. The master generated NACK before the end of a read operation is also automatically generated after
START BY
MASTER
FRAME 1
Default
0
0
A3
A2
Default
0
0
0
0
0
0
0
A6
1
2
A1
C read and write operations, respectively. Note that the LSB of the I2CADR register is used to select
Description
Address of the I
Command Bit for Read or Write. When this bit is set to Logic 1, a read command is transmitted on the I
bus. Data from slave in the SPI2CRx SFR is expected after command byte. When this bit is set to Logic 0, a
write command is transmitted on the I
A5
SERIAL BUS ADDRESS BYTE
A0
A4
Description
This bit is set to Logic 1 when the I
I
does not send an acknowledgement. The I
Write a 0 to this bit to clear it.
I
Write a 0 to this bit to clear it.
I
Write a 0 to this bit to clear it.
Status Bits for 3- or 4-Bytes Deep I
used in I
I2CFIFOSTAT[1:0]
00
01
10
11
Set when trying to write and read at the same time. Write a 0 to this bit to clear it.
Set when write was attempted when I
R/W
2
2
2
C No Acknowledgement Transmit Interrupt. This bit is set to Logic 1 when the slave device
C Receive Interrupt. This bit is set to Logic 1 when the receive FIFO is not empty.
C Transmit Interrupt. This bit is set to Logic 1 when the transmit FIFO is empty.
ACK BY
SLAVE
FRAME 1
A3
9
A2
2
D7
C communication (receive or transmit) because only one FIFO is active at a time.
1
2
.
C Slave Being Addressed. Writing to this register starts the I
A1
D6
DATA BYTE 1 FROM MASTER
Figure 99. I
Figure 98. I
A0
D5
Rev. PrA | Page 126 of 136
R/W
D4
ACK BY
SLAVE
FRAME 2
Result
FIFO empty
Reserved
FIFO half full
FIFO full
D3
2
2
9
C Read Operation
C Write Operation
D2
D7
1
2
C bus. Data to slave is expected in the SPI2CTx SFR.
2
D1
D6
2
C FIFO. The FIFO monitored in these 2 bits is the one currently
C interface is used. When set, the Tx FIFO is emptied
DATA BYTE 1 FROM MASTER
D0
2
D5
C transmit FIFO was full. Write a 0 to this bit to clear it.
ACK BY
MASTER
2
9
D4
C communication is stopped after this event.
FRAME 2
D3
D2
D7
1
Preliminary Technical Data
D6
D1
DATA BYTE N FROM SLAVE
D5
D0
ACK BY
SLAVE
D4
9
FRAME N + 1
2
D3
C transmission (read or write).
STOP BY
MASTER
D2
D1
D0
NACK BY
MASTER
9
STOP BY
MASTER
2
C