KM432S2030CT-F10 SAMSUNG [Samsung semiconductor], KM432S2030CT-F10 Datasheet - Page 8

• Manufacturer Part Number: KM432S2030CT-F10
• Description: 2M x 32 SDRAM 512K x 32bit x 4 Banks Synchronous DRAM LVTTL
• Manufacturer: SAMSUNG [Samsung semiconductor]

KM432S2030C
AC CHARACTERISTICS
Note :
CLK cycle time
CLK to valid
output delay
Output data
CLK high pulse width
CLK low pulse width
Input setup time
Input hold time
CLK to output in Low-Z
CLK to output
in Hi-Z
1. Parameters depend on programmed CAS latency.
2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.
3. Assumed input rise and fall time (tr & tf)=1ns.
2. Minimum delay is required to complete write.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
5. For -6/7/8/10, tRDL=1CLK product can be supported within restricted amounts and it will be distinguished by bucket code
If tr & tf is longer than 1ns, transient time compensation should be considered,
i.e., [(tr + tf)/2-1]ns should be added to the parameter.
"NV"
Parameter
CAS Latency=3
CAS Latency=2
CAS Latency=3
CAS Latency=2
CAS Latency=3
CAS Latency=2
CAS Latency=3
CAS Latency=2
CAS Latency=3
CAS Latency=2
CAS Latency=3
CAS Latency=2
CL
t
t
t
t
t
t
t
CC(min)
RRD(min)
RCD(min)
RP(min)
RAS(min)
RAS(max)
RC
Symbol
(
(AC operating conditions unless otherwise noted)
min
)
11
3
6
3
3
7
Symbol
-6
t
t
t
t
t
SAC
t
t
t
t
SHZ
SLZ
CC
OH
CH
SS
SH
CL
-
-
-
-
-
-
10
3
7
3
3
7
Min
2.5
2.5
2.5
1.5
6
1
1
-
-
-
-
-
-
-
-
-7
-6
Version
1000
-
-
-
-
-
-
Max
5.5
5.5
100
- 8 -
-
-
-
-
-
-
-
-
2
3
8
3
3
6
9
1.75
Min
2.5
7
3
3
1
1
-8
-
-
-
-
-
-
10
-7
2
2
2
5
7
1000
Max
5.5
5.5
-
-
-
-
-
-
-
-
10
3
2
2
5
7
-10
Min
2.5
10
8
3
3
2
1
1
12
-
-
-
2
2
2
4
6
-
-8
1000
Max
Unit
CLK
CLK
CLK
CLK
CLK
CLK
ns
us
6
7
6
7
-
-
-
-
-
-
Min
2.5
3.5
3.5
2.5
10
12
1
1
-
-
-
-
REV. 1.1 Mar. '99
-10
CMOS SDRAM
1000
Max
7
8
7
8
-
-
-
-
-
-
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note
1, 2
1
2
3
3
3
3
2