KM432S2030CT-F10 SAMSUNG [Samsung semiconductor], KM432S2030CT-F10 Datasheet - Page 10

• Manufacturer Part Number: KM432S2030CT-F10
• Description: 2M x 32 SDRAM 512K x 32bit x 4 Banks Synchronous DRAM LVTTL
• Manufacturer: SAMSUNG [Samsung semiconductor]

KM432S2030C
Register Programmed with MRS
POWER UP SEQUENCE
MODE REGISTER FIELD TABLE TO PROGRAM MODES
1. Apply power and start clock, Attempt to maintain CKE= "H", DQM= "H" and the other pins are NOP condition at the inputs.
2. Maintain stable power, stable clock and NOP input condition for a minimum of 200us.
3. Issue precharge commands for all banks of the devices.
4. Issue 2 or more auto-refresh commands.
5. Issue a mode register set command to initialize the mode register.
cf.) Sequence of 4 & 5 is regardless of the order.
The device is now ready for normal operation.
Note : 1. If A
Address
Function
A
A
0
0
1
1
0
1
8
9
2. RFU (Reserved for future use) should stay "0" during MRS cycle.
Write Burst Length
BA
A
0
1
0
1
7
9
0
RFU
Test Mode
is high during MRS cycle, "Burst Read Single Bit Write" function will be enabled.
~ BA
Mode Register Set
Single Bit
Length
1
Burst
Reserved
Reserved
Reserved
A
Type
RFU
10
/AP
W.B.L
A
9
A
0
0
0
0
1
1
1
1
6
A
A
CAS Latency
0
0
1
1
0
0
1
1
8
5
TM
A
0
1
0
1
0
1
0
1
4
A
7
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Latency
2
3
- 10
A
6
CAS Latency
A
0
1
3
Burst Type
A
5
Sequential
Interleave
Type
A
4
A
0
0
0
0
1
1
1
1
2
A
BT
3
A
0
0
1
1
0
0
1
1
Full Page Length : x32 (256)
1
REV. 1.1 Mar. '99
CMOS SDRAM
A
A
Burst Length
0
1
0
1
0
1
0
1
0
2
Reserved
Reserved
Reserved
Full Page
Burst Length
BT = 0
1
2
4
8
A
1
Reserved
Reserved
Reserved
Reserved
BT = 1
A
1
2
4
8
0