KM432S2030CT-F10 SAMSUNG [Samsung semiconductor], KM432S2030CT-F10 Datasheet - Page 31

• Manufacturer Part Number: KM432S2030CT-F10
• Description: 2M x 32 SDRAM 512K x 32bit x 4 Banks Synchronous DRAM LVTTL
• Manufacturer: SAMSUNG [Samsung semiconductor]

CLOCK
KM432S2030C
Page Write Cycle at Different Bank @Burst Length=4
A
ADDR
10
DQM
CKE
RAS
CAS
BA
BA
WE
/AP
DQ
CS
0
1
*Note :
0
Row Active
(A-Bank)
RAa
RAa
1
1. To interrupt burst write by Row precharge, DQM should be asserted to mask invalid input data.
2. To interrupt burst write by Row precharge, both the write and the precharge banks must be the same.
3.For -6/7/8/10, tRDL=1CLK product can be supported within restricted amounts and it will be distinguished by bucket code "NV"
. From the next generation, tRDL will be only 2CLK for every clock frequency
2
Row Active
(B-Bank)
RBb
RBb
3
(A-Bank)
Write
DAa0 DAa1 DAa2
CAa
4
5
6
DAa3
7
tCDL
(B-Bank)
Write
DBb0 DBb1 DBb2 DBb3
CBb
Row Active
8
(C-Bank)
RCc
RCc
9
HIGH
10
Row Active
(D-Bank)
RDd
RDd
11
(C-Bank)
Write
DCc0 DCc1 DDd0 DDd1 DDd2
CCc
12
13
(D-Bank)
Write
CDd
14
15
REV. 1.1 Mar. '99
CMOS SDRAM
16
*Note 1
tRDL
17
*Note 2
*Note 3
(All Banks)
Precharge
18
: Don't care
19