KM432S2030CT-F10 SAMSUNG [Samsung semiconductor], KM432S2030CT-F10 Datasheet - Page 39

• Manufacturer Part Number: KM432S2030CT-F10
• Description: 2M x 32 SDRAM 512K x 32bit x 4 Banks Synchronous DRAM LVTTL
• Manufacturer: SAMSUNG [Samsung semiconductor]

DQ
CLOCK
KM432S2030C
Burst Read Single bit Write Cycle @Burst Length=2
A
ADDR
DQM
10
CKE
RAS
CAS
BA
BA
WE
/AP
CS
CL=2
CL=3
0
1
*Note :
0
*Note 1
Row Active
(A-Bank)
RAa
RAa
1
1. BRSW modes is enabled by setting A
2. When BRSW write command with auto precharge is executed, keep it in mind that t
At the BRSW Mode, the burst length at write is fixed to "1" regardless of programmed burst length.
Auto precharge is executed at the burst-end cycle, so in the case of BRSW write command,
the next cycle starts the precharge.
2
3
(A-Bank)
Write
DAa0
DAa0
CAa
4
Row Active
(B-Bank)
RBb
RBb
Auto Precharge
5
Read with
(A-Bank)
CAb
6
7
9
"High" at MRS (Mode Register Set).
QAb0 QAb1
8
QAb0 QAb1
9
HIGH
10
Row Active
(C-Bank)
RCc
RAc
11
Auto Precharge
12
Write with
(B-Bank)
DBc0
DBc0
CBc
13
*Note 2
14
RAS
(C-Bank)
should not be violated.
Read
CCd
15
REV. 1.1 Mar. '99
CMOS SDRAM
16
QCd0 QCd1
17
QCd0 QCd1
18
Precharge
(C-Bank)
: Don't care
19