KM432S2030CT-F10 SAMSUNG [Samsung semiconductor], KM432S2030CT-F10 Datasheet - Page 7

• Manufacturer Part Number: KM432S2030CT-F10
• Description: 2M x 32 SDRAM 512K x 32bit x 4 Banks Synchronous DRAM LVTTL
• Manufacturer: SAMSUNG [Samsung semiconductor]

(AC operating conditions unless otherwise noted)
OPERATING AC PARAMETER
CLK cycle time
Row active to row active delay
RAS to CAS delay
Row precharge time
Row active time
Row cycle time
Last data in to row precharge
Last data in to new col.address delay
Last data in to burst stop
Col. address to col. address delay
Mode Register Set cycle time
Number of valid output data
KM432S2030C
AC OPERATING TEST CONDITIONS
Note :
Notes :
AC input levels (Vih/Vil)
Input timing measurement reference level
Input rise and fall time
Output timing measurement reference level
Output load condition
Output
1. The DC/AC Test Output Load of KM432S2030C-6/7 is 30pF.
2. The VDD condition of KM432S2030C-6 is 3.135V~3.6V.
1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then
(Fig. 1) DC output load circuit
rounding off to the next higher integer. Refer to the following clock unit based AC conversion table
870
Parameter
Parameter
CAS Latency=3
CAS Latency=2
3.3V
1200
50pF
*1
t
t
t
t
t
t
t
t
t
t
t
t
Symbol
CC(min)
RRD(min)
RCD(min)
RP(min)
RAS(min)
RAS(max)
RC
RDL(min)
CDL(min)
BDL(min)
CCD(min)
MRS(min)
V
V
(
min
OH
OL
)
(DC) = 0.4V, I
(DC) = 2.4V, I
(V
DD
= 3.3V
12
18
18
42
66
-6
6
OL
OH
0.3V, T
- 7 -
= 2mA
= -2mA
A
= 0 to 70 C)
14
18
18
49
67
-7
7
See Fig. 2
tr/tf = 1/1
2.4/0.4
Value
Version
1.4
1.4
Output
100
2
1
1
1
2
2
1
16
18
18
48
68
-8
8
(Fig. 2) AC output load circuit
Z0 = 50
-10
10
20
20
20
50
70
REV. 1.1 Mar. '99
CMOS SDRAM
Unit
CLK
CLK
CLK
CLK
CLK
ns
ns
ns
ns
ns
us
ns
ea
Vtt = 1.4V
Unit
50
ns
50pF
V
V
V
Note
*1
2,5
1
1
1
1
1
2
2
3
4