KM432S2030CT-F10 SAMSUNG [Samsung semiconductor], KM432S2030CT-F10 Datasheet - Page 36

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KM432S2030CT-F10

Manufacturer Part Number
KM432S2030CT-F10
Description
2M x 32 SDRAM 512K x 32bit x 4 Banks Synchronous DRAM LVTTL
Manufacturer
SAMSUNG [Samsung semiconductor]
Datasheet
CLOCK
KM432S2030C
Clock Suspension & DQM Operation Cycle @CAS Latency=2, Burst Length=4
A
ADDR
10
DQM
CKE
RAS
CAS
/AP
BA
BA
WE
DQ
CS
0
1
*Note : 1. DQM is needed to prevent bus contention.
0
Row Active
Ra
Ra
1
2
Read
Ca
3
4
Qa0
5
Suspension
Clock
Qa1
6
7
Qa2
8
Qa3
tSHZ
9
Read
Cb
10
11
Qb0
12
Read DQM
*Note 1
Qb1
tSHZ
13
14
Write
Dc0
Cc
15
Write
DQM
REV. 1.1 Mar. '99
CMOS SDRAM
16
Suspension
Clock
Dc2
17
18
: Don't care
Write
DQM
19

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