KM432S2030CT-F10 SAMSUNG [Samsung semiconductor], KM432S2030CT-F10 Datasheet
KM432S2030CT-F10
Related parts for KM432S2030CT-F10
KM432S2030CT-F10 Summary of contents
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... KM432S2030C SDRAM Samsung Electronics reserves the right to change products or specification without notice. 512K x 32bit x 4 Banks Synchronous DRAM LVTTL Revision 1.1 March 1999 - 1 - CMOS SDRAM REV. 1.1 Mar. '99 ...
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... Removed KM432S2030C-7@CL2 part (115MHz@CL2) • Changed VDD condition of KM432S2030C-8@CL2 from 3.135V to 3.0V~3.6V. • Changed AC Characteristic table format • Add KM432S2030C-Z part. Revision 0.1 (December 2nd, 1998) • Delete refresh information(4K/64ms) Revision 0.0 (November 20th, 1998) • Define target specification CMOS SDRAM REV. 1.1 Mar. '99 ...
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... ORDERING INFORMATION KM432S2030CT-G/F6 KM432S2030CT-G/F7 KM432S2030CT-G/F8 KM432S2030CT-G/F10 Data Input Register Column Decoder Latency & Burst Length Programming Register LWE LCAS Timing Register ...
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... SSQ DDQ SSQ DDQ CMOS SDRAM V SS DQ15 V SSQ DQ14 DQ13 V DDQ DQ12 DQ11 V SSQ DQ10 DQ9 V DDQ DQ8 N DQM1 N.C N.C CLK CKE DQM3 ...
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... V IN OUT DDQ T STG 1MHz 1.4V 200 mV) A REF Symbol C CLK ADD C OUT - 5 - CMOS SDRAM Input Function , Column address : after the clock and masks the output. Value -1.0 ~ 4.6 -1.0 ~ 4.6 -55 ~ +150 1 50 Min Max 2.5 4 2.5 4.5 2.5 4.5 4.0 6.5 REV. 1.1 Mar. '99 Unit ...
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... Active standby current in non power-down mode (One bank active CC3 Operating current I CC4 (Burst mode) Refresh current I CC5 Self refresh current I CC6 Notes : 1. Measured with outputs open. 2. Refresh period is 64ms. 3. KM432S2030CT-G** 4. KM432S2030CT-F Symbol Min 3.0 DD DDQ 2.4 ...
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... RRD(min RCD(min RP(min RAS(min) t RAS(max min t RDL(min) t CDL(min) t BDL(min) t CCD(min) t MRS(min CMOS SDRAM = Value 2.4/0.4 1.4 tr/tf = 1/1 1.4 See Fig. 2 Output (Fig output load circuit Version - 100 ...
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... 5.5 t SAC - - t 2.5 - 2 1.5 1. SLZ - 5.5 t SHZ - - - 8 - CMOS SDRAM Unit -8 - CLK CLK CLK CLK CLK CLK -7 -8 -10 Max Min Max Min Max 1000 1000 1000 - ...
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... MRS can be issued only at all banks precharge state. A new command can be issued after 2 CLK cycles of MRS. 3. Auto refresh functions are as same as CBR refresh of DRAM. The automatical precharge without row precharge command is meant by "Auto". Auto/self refresh can be issued only at all banks precharge state. ...
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... Reserved Reserved Reserved Reserved Reserved Reserved - 10 CMOS SDRAM Burst Type Burst Length A Type Sequential Interleave ...
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... CMOS SDRAM Interleave Interleave ...
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... KM432S2030C DEVICE OPERATIONS CLOCK (CLK) The clock input is used as the reference for all SDRAM opera- tions. All operations are synchronized to the positive going edge of the clock. The clock transitions must be monotonic between V and V . During operation with CKE high all inputs are ...
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... Also the noise generated during sensing of each bank of SDRAM is high, requiring some time for power supplies to recover before another bank can be sensed reliably. t ...
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... SDRAM. The self refresh is the preferred refresh mode for data retention and low power operation of SDRAM. In self refresh mode, the SDRAM disables the internal clock and all the input buffers except CKE. The refresh addressing and timing are internally generated to reduce power consumption. ...
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... Clock Suspended During Read (BL=4) Masked by CKE Not Written 2) Read Mask (BL=4) Masked byDQM Note 2 Hi-Z Hi Hi-Z Hi CMOS SDRAM RD Masked by CKE Suspended Dout RD Masked by DQM Hi Hi-Z Q ...
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... Last data in to new column address delay. (=1CLK) CDL Note Write interrupted by Read (BL=2) WR DQ(CL2 DQ(CL3 CMOS SDRAM RD tCCD Note tCDL Note 3 REV. 1.1 Mar. '99 ...
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... Note Hi Hi Note CMOS SDRAM REV. 1.1 Mar. '99 ...
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... Masked by DQM 2) Normal Read (BL=4) PRE DQ(CL2) tRDL Note 1,4 DQ(CL3) 2) Normal Read (BL= DQ(CL2) Note 3,4 DQ(CL3) Auto Precharge Starts - 18 CMOS SDRAM CLK CMD CLK CMD from this point. RP REV. 1.1 Mar. '99 Note 2 PRE ...
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... Write Burst Stop (BL=8) PRE tRDL Note 1,5 4) Read Burst Stop (BL=4) PRE Note MRS ACT tRP 2CLK - 19 CMOS SDRAM CLK WR CMD DQM CLK CMD RD STOP DQ(CL2 DQ(CL3) Q REV. 1.1 Mar. '99 STOP ...
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... CKE *Note : 1. Active power down : one or more banks active state. 2. Precharge power down : all banks precharge state. 3. The auto refresh is the same as CBR refresh of conventional DRAM. No precharge commands are required after auto refresh command. During t from auto refresh command, any other command can not be accepted. ...
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... See the BURST SEQUENCE TABLE. (BL= BL= BL=1, 2 Interleave Counting = Sequential Counting Every cycle Read/Write Command with random column address can realize Random Column Access. That is similar to Extended Data Out (EDO) Operation of conventional DRAM. At MRS A = "000". 2,1,0 At auto precharge, t should not be violated. ...
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... X X ILLEGAL NOP --> Idle after NOP --> Idle after ILLEGAL ILLEGAL ILLEGAL /AP NOP --> Idle after CMOS SDRAM ACTION Note REV. 1.1 Mar. ' ...
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... NOP --> Idle after ILLEGAL ILLEGAL ILLEGAL NOP --> Idle after 2 clocks NOP --> Idle after 2 clocks ILLEGAL ILLEGAL ILLEGAL BA = Bank Address CA = Column Address AP = Auto Precharge - 23 CMOS SDRAM ACTION RCD RCD RFC RFC /AP). 10 REV. 1.1 Mar. '99 Note ...
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... must be satisfied before any command other than exit CMOS SDRAM ACTION INVALID Exit Self Refresh --> Idle after t (ABI) RFC Exit Self Refresh --> Idle after t (ABI) RFC ILLEGAL ILLEGAL ILLEGAL NOP (Maintain Self Refresh) INVALID Exit Power Down --> ABI Exit Power Down --> ...
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... Ca Cb *Note 2 *Note 3 tSH tSAC Qa Db tSLZ tSS tOH tSH tSS tSS tSH Write CMOS SDRAM tRP Cc Rb *Note 2,3 *Note 4 *Note *Note 3 *Note Read Row Active Precharge REV. 1.1 Mar. '99 ...
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... Enable auto precharge, precharge bank B at end of burst Enable auto precharge, precharge bank C at end of burst Enable auto precharge, precharge bank D at end of burst. BA0 BA1 Precharge 0 0 Bank Bank Bank Bank All Banks CMOS SDRAM REV. 1.1 Mar. ' ...
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... Auto Refresh CMOS SDRAM ¡ó tRC ¡ó ¡ó ¡ó ¡ó ...
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... Read (A-Bank) (A-Bank) *Note : 1. Minimum row cycle times is required to complete internal DRAM operation. 2. Row precharge can interrupt burst on any cycle. [CAS Latency - 1] number of valid output data is available after Row precharge. Last valid output will be Hi-Z(t 3. Access time from Row active command Ouput will be Hi-Z after the end of burst. ( & ...
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... HIGH Cb Qa0 Qa1 Qb0 Qb1 Qb2 Qa0 Qa1 Qb0 Qb1 *Note 1 Read (A-Bank) before Row precharge, will be written. RDL CMOS SDRAM *Note tRDL *Note 4 Dc0 Dc1 Dd0 Dd1 Dc0 Dc1 Dd0 Dd1 tCDL *Note 3 ...
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... QAa0 QAa1 QAa2 QBb0 QBb1 QBb2 QCc0 QCc1 QCc2 QDd0 QDd1 QDd2 QAa0 QAa1 QAa2 QBb0 Read Read (B-Bank) (C-Bank) Row Acive Row Active (C-Bank) (D-Bank) Precharge (A-Bank) CMOS SDRAM CDd QBb1 QBb2 QCc0 QCc1 QCc2 QDd0 QDd1 QDd2 Read Precharge (D-Bank) ...
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... HIGH CBb RCc RCc DAa3 DBb0 DBb1 DBb2 DBb3 tCDL Write Row Active (B-Bank) Row Active (C-Bank) CMOS SDRAM RDd CCc CDd RDd DCc0 DCc1 DDd0 DDd1 DDd2 tRDL *Note 1 Write (D-Bank) (D-Bank) Write (C-Bank) REV ...
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... CDL HIGH RDb RBb QAa0 QAa1 QAa2 QAa3 QAa0 QAa1 QAa2 QAa3 Precharge (A-Bank) Row Active (D-Bank) CMOS SDRAM CDb RBc CBc RAc *Note 1 tCDL DDb0 DDb1 DDb2 DDb3 DDb0 DDb1 DDb2 DDb3 Write Read ...
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... HIGH CAa QAa0 QAa1 QAa2 QAa3 QAa0 QAa1 QAa2 QAa3 Read with Auto Precharge Auto Precharge Start Point (A-Bank) (A-Bank) t before internal precharge start. RAS CMOS SDRAM CBb DBb0 DBb1 DBb2 DBb3 DBb0 DBb1 DBb2 DBb3 Auto Precharge ...
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... Ca Cb Qa0 Qa1 Qb0 Qb1 Qa0 Qa1 Qb0 Read without Auto Read with precharge(B-Bank) Auto Pre Auto Precharge charge Start Point (A-Bank) (A-Bank)* CMOS SDRAM Qb2 Qb3 Qb1 Qb2 Qb3 Precharge Row Active (B-Bank) (A-Bank) REV. 1.1 Mar. '99 ...
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... Qa0 Qa1 Qa2 Qa3 Qa0 Qa1 Qa2 * Read with Auto Precharge Start Point Auto Precharge (A-Bank) (A-Bank) Row Active (B-Bank) CMOS SDRAM Qb0 Qb1 Qb2 Qb3 Qa3 Qb0 Qb1 Qb2 Read with Auto Precharge Start Point Auto Precharge ...
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... DQM Row Active Read *Note : 1. DQM is needed to prevent bus contention Qa0 Qa1 Qa2 Qa3 tSHZ Clock Read Suspension CMOS SDRAM Qb0 Qb1 Dc0 Dc2 tSHZ *Note 1 Write Read DQM DQM Write Clock Suspension REV ...
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... Burst stop is valid at every burst length HIGH QAa0 QAa1 QAa2 QAa3 QAa4 QAa0 QAa1 QAa2 QAa3 QAa4 Burst Stop CMOS SDRAM CAb 1 QAb0 QAb1 QAb2 QAb3 QAb4 QAb5 2 QAb0 QAb1 QAb2 QAb3 QAb4 QAb5 Read (A-Bank) REV ...
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... For -6/7/8/10, tRDL=1CLK product can be supported within restricted amounts and it will be distinguished by bucket code "NV" . From the next generation, tRDL will be only 2CLK for every clock frequency HIGH tBDL Burst Stop CMOS SDRAM CAb *Note 2,4 DAb0 DAb1 DAb2 DAb3 DAb4 DAb5 Write (A-Bank) REV ...
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... HIGH RBb CAb RBb QAb0 QAb1 QAb0 QAb1 Row Active Row Active (B-Bank) Read with Auto Precharge (A-Bank) "High" at MRS (Mode Register Set). 9 CMOS SDRAM *Note 2 RCc CBc CCd RAc DBc0 DBc0 Read (C-Bank) (C-Bank) Write with ...
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... Ra ¡ó ¡ó ¡ó ¡ó ¡ó ¡ó Row Active Active Precharge Active Power-down Power-down Power-down Exit Entry CMOS SDRAM *Note 2 Ca tSHZ Qa0 Qa1 Qa2 Read Precharge Exit REV. 1.1 Mar. '99 17 ...
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... Self Refresh Exit RAS CMOS SDRAM ¡ó *Note 4 tRCmin *Note 6 ¡ó ¡ó *Note 5 ¡ ...
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... CS, RAS, CAS, & WE activation at the same clock cycle with address key will set internal mode register. 2. Minimum 2 clock cycles should be met before new RAS activation. 3. Please refer to Mode Register Set table. Auto Refresh Cycle Auto Refresh CMOS SDRAM ¡ ...
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... KM432S2030C PACKAGE DIMENSIONS 86-TSOP2-400F #86 #1 0.10 MAX 0.004 0. 0.024 #44 #43 22.62 MAX 0.891 22.22 0.10 0.21 0.875 0.008 0.004 0.50 +0.10 0.20 0.0197 -0. CMOS SDRAM Unit : Millimeters 0.25 TYP 0.010 +0.075 0.125 -0.035 +0.003 0.005 -0.001 1.00 1.20 0.05 0.10 MAX 0.002 0.039 0.047 0.004 0.05 MIN 0.010 REV. 1.1 Mar. '99 0~8 C ...