S71GL256NB0 SPANSION [SPANSION], S71GL256NB0 Datasheet - Page 25

• Manufacturer Part Number: S71GL256NB0
• Description: Stacked Multi-chip Product (MCP)
• Manufacturer: SPANSION [SPANSION]

June 14, 2004 S29GLxxxN_00_A4
Standby Mode
Automatic Sleep Mode
RESET#: Hardware Reset Pin
Accelerated Program Operation
The device offers accelerated program operations through the ACC function. This
is one of two functions provided by the WP#/ACC pin. This function is primarily
intended to allow faster manufacturing throughput at the factory.
If the system asserts V
mentioned Unlock Bypass mode, temporarily unprotects any protected sector
groups, and uses the higher voltage on the pin to reduce the time required for
program operations. The system would use a two-cycle program command se-
quence as required by the Unlock Bypass mode. Removing V
ACC pin returns the device to normal operation. Note that the WP#/ACC pin must
not be at V
age may result. WP# has an internal pullup; when unconnected, WP# is at V
Autoselect Functions
If the system writes the autoselect command sequence, the device enters the au-
toselect mode. The system can then read autoselect codes from the internal
register (which is separate from the memory array) on DQ7–DQ0. Standard read
cycle timings apply in this mode. Refer to the “Autoselect Command Sequence”
section on page 50 sections for more information.
When the system is not reading or writing to the device, it can place the device
in the standby mode. In this mode, current consumption is greatly reduced, and
the outputs are placed in the high impedance state, independent of the OE#
input.
The device enters the CMOS standby mode when the CE# and RESET# pins are
both held at V
V
will be in the standby mode, but the standby current will be greater. The device
requires standard access time (t
of these standby modes, before it is ready to read data.
If the device is deselected during erasure or programming, the device draws ac-
tive current until the operation is completed.
Refer to the “DC Characteristics” section on page 78 for the standby current
specification.
The automatic sleep mode minimizes Flash device energy consumption. The de-
vice automatically enables this mode when addresses remain stable for t
30 ns. The automatic sleep mode is independent of the CE#, WE#, and OE# con-
trol signals. Standard address access timings provide new data when addresses
are changed. While in sleep mode, output data is latched and always available to
the system. Refer to the “DC Characteristics” section on page 78 for the
automatic sleep mode current specification.
The RESET# pin provides a hardware method of resetting the device to reading
array data. When the RESET# pin is driven low for at least a period of t
device immediately terminates any operation in progress, tristates all output
pins, and ignores all read/write commands for the duration of the RESET# pulse.
The device also resets the internal state machine to reading array data. The op-
IH
.) If CE# and RESET# are held at V
HH
A d v a n c e
for operations other than accelerated programming, or device dam-
IO
± 0.3 V. (Note that this is a more restricted voltage range than
HH
S29GLxxxN MirrorBit
on this pin, the device automatically enters the afore-
I n f o r m a t i o n
CE
) for read access when the device is in either
IH
, but not within V
TM
Flash Family
IO
± 0.3 V, the device
HH
from the WP#/
RP
ACC
, the
IH
+
.
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