S71GL256NB0 SPANSION [SPANSION], S71GL256NB0 Datasheet - Page 128

• Manufacturer Part Number: S71GL256NB0
• Description: Stacked Multi-chip Product (MCP)
• Manufacturer: SPANSION [SPANSION]

Functional Description
Legend:L = V
Notes:
1. Should not be kept this logic condition longer than 1ms. Please contact local Spansion representative for the relaxation of
2. Power Down mode can be entered from Standby state and all DQ pins are in High-Z state. Data retention depends on the
3. Can be either V
4. OE# can be V
Power Down (for 32M, 64M Only)
128
Standby (Deselect)
Output Disable (Note 1)
Output Disable (No Read)
Read (Upper Byte)
Read (Lower Byte)
Read (Word)
No Write
Write (Upper Byte)
Write (Lower Byte)
Write (Word)
Power Down
1ms limitation.
selection of Power Down Program, 16M has data retetion in all modes except Power Down. Refer to POWER DOWN for the
detail.
(1) Write pulse is initiated by CE1# (refer to CE1# Controlled Write timing), or cycle time of the previous operation cycle is
satisfied.
(2) OE# stays V
Sleep (default)
4M Partial
8M Partial
Power Down
Mode
Mode
IL
IL
, H = V
The Power Down is low power idle state controlled by CE2. CE2 Low drives the
device in power down mode and maintains low power idle state as long as CE2 is
kept Low. CE2 High resumes the device from power down mode. These devices
have three power down mode. These can be proammed by series of read/write
operation. Each mode has follwoing features.
Pin Name
IL
during Write operation if the following conditions are satisfied:
IL
or V
V
during Write cycle
SS
Retention Data
IH
IH
4M bit
8M bit
but must be valid before Read or Write.
, X can be either V
No
32M
CE2#
Ground
H
H
L
00000h to 3FFFFh
00000h to 7FFFFh
Retention Address
CE1#
H
X
L
N/A
A d v a n c e
IL
or V
WE#
X
H
H
X
L
pSRAM Type 7
IH
, High-Z = High Impedence.
H (Note 4)
OE#
X
H
X
L
Sleep (default)
16M Partial
8M Partial
I n f o r m a t i o n
Mode
Description
LB#
X
X
H
H
H
H
X
L
L
L
L
UB#
H
H
H
H
X
X
L
L
L
L
X
Retention Data
16M bit
8M bit
Note 3
A
No
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
21-0
X
X
64M
Output Valid
Output Valid
pSRAM_Type07_13_A0 May 4, 2004
Input Valid
Input Valid
High-Z
High-Z
High-Z
High-Z
Invalid
Invalid
High-Z
00000h to 7FFFFh
DQ
00000h to FFFFFh
Retention Address
8-1
N/A
Output Valid
Output Valid
Input Valid
Input Valid
DQ
High-Z
High-Z
High-Z
High-Z
Invalid
Invalid
High-Z
16-9