S71GL256NB0 SPANSION [SPANSION], S71GL256NB0 Datasheet - Page 143

• Manufacturer Part Number: S71GL256NB0
• Description: Stacked Multi-chip Product (MCP)
• Manufacturer: SPANSION [SPANSION]

Notes:
1. This timing diagram assumes CE2=H.
2. OE# can be fixed Low during write operation if it is CE1# controlled write at Read-Write-Read sequence.
Notes:
1. This timing diagram assumes CE2=H.
2. CE1# can be tied to Low for WE# and OE# controlled operation.
May 4, 2004 pSRAM_Type07_13_A0
ADDRESS
UB#, LB#
ADDRESS
UB#, LB#
CE1#
DQ
WE#
CE1#
DQ
OE#
WE#
OE#
READ DATA OUTPUT
READ DATA OUTPUT
Low
t
t
OHAH
CHAH
Figure 45. Read / Write Timing #1-2 (CE1#/WE#/OE# Control)
t
OES
t
CP
t
t
Figure 46. Read / Write Timing #2 (OE#, WE# Control)
A d v a n c e
OH
OH
t
t
t
CHZ
OHCL
OHZ
t
AS
t
AS
WRITE ADDRESS
WRITE ADDRESS
t
t
I n f o r m a t i o n
WC
WP
WRITE DATA INPUT
t
t
WC
WP
t
DS
WRITE DATA INPUT
pSRAM Type 7
t
DS
t
t
WR
DH
t
t
WR
DH
t
WHOL
t
CP
t
ASO
t
ASC
t
OLZ
READ ADDRESS
t
AA
t
t
OE
OLZ
READ ADDRESS
t
RC
t
CE
READ DATA OUTPUT
t
READ DATA OUTPUT
OE
t
RC
t
OHAH
t
t
OH
t
t
OHZ
OH
CHAH
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