S71GL256NB0 SPANSION [SPANSION], S71GL256NB0 Datasheet - Page 139

• Manufacturer Part Number: S71GL256NB0
• Description: Stacked Multi-chip Product (MCP)
• Manufacturer: SPANSION [SPANSION]

Notes:
1. This timing diagram assumes CE2=H and WE#=H.
2. Either or both LB# and UB# must be Low when both CE1# and OE# are Low.
Note: This timing diagram assumes CE2=H.
May 4, 2004 pSRAM_Type07_13_A0
ADDRESS
ADDRESS
ADDRESS
(A21-A3)
(Output)
LB#/UB#
(A2-A0)
(Input)
LB#, UB#
CE1#
OE#
DQ
CE1#
DQ
WE#
OE#
Write Timings
Low
Figure 37. Read Timing #5 (Random and Page Address Access for 32M and
t
ASO
ADDRESS
A d v a n c e
t
t
t
OLZ
BLZ
AA
VALID
t
OHCL
t
t
OE
BA
t
t
RC
AS
t
ADDRESS VALID
AS
Figure 38. Write Timing #1 (Basic Timing)
t
AS
t
RC
VALID DATA OUTPUT
t
OH
(Normal Access)
I n f o r m a t i o n
ADDRESS
VALID
t
PAA
pSRAM Type 7
t
ADDRESS VALID
PRC
64M Only)
t
CW
t
WP
t
t
WC
BW
t
AX
t
OH
VALID DATA INPUT
t
DS
ADDRESS
t
VALID
AA
t
RC
ADDRESS VALID
VALID DATA OUTPUT
t
DH
t
t
t
(Page Access)
WR
WR
WR
t
RC
t
OH
t
t
t
WHP
BHP
CP
ADDRESS
t
VALID
PAA
t
PRC
t
AS
t
AS
t
AS
t
t
Ax
OH
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