S71GL256NB0 SPANSION [SPANSION], S71GL256NB0 Datasheet - Page 142

• Manufacturer Part Number: S71GL256NB0
• Description: Stacked Multi-chip Product (MCP)
• Manufacturer: SPANSION [SPANSION]

Note: This timing diagram assumes CE2=H and OE#=H.
Notes:
1. This timing diagram assumes CE2=H.
2. Write address is valid from either CE1# or WE# of last falling edge.
142
ADDRESS
ADDRESS
UB#, LB#
DQ9-16
DQ1-8
(Input)
(Input)
CE1#
WE#
CE1#
DQ
UB#
WE#
Read/Write Timings
OE#
LB#
READ DATA OUTPUT
Low
t
CHAH
Figure 43. Write Timing #3-4 (WE#/LB#/UB# Byte Write Control)
t
CP
t
OH
t
t
CHZ
t
OHCL
AS
t
Figure 44. Read/Write Timing #1-1 (CE1# Control)
AS
t
AS
ADDRESS VALID
t
WRITE ADDRESS
BWO
t
BW
t
WC
DATA INPUT
t
BW
A d v a n c e
t
DS
DATA INPUT
VALID
t
DS
t
t
CW
VALID
WC
pSRAM Type 7
WRITE DATA INPUT
t
DH
t
t
WR
t
DS
t
DH
WR
t
t
I n f o r m a t i o n
WR
t
BHP
BHP
t
DH
t
CP
t
AS
t
AS
t
ASC
ADDRESS VALID
t
CLZ
t
BW
t
t
WC
READ ADDRESS
BWO
DATA INPUT
t
t
BW
CE
t
DS
DATA INPUT
VALID
t
DS
VALID
pSRAM_Type07_13_A0 May 4, 2004
t
RC
t
DH
t
WR
t
t
DH
WR
t
CHAH
t
OH