S71GL256NB0 SPANSION [SPANSION], S71GL256NB0 Datasheet - Page 123

• Manufacturer Part Number: S71GL256NB0
• Description: Stacked Multi-chip Product (MCP)
• Manufacturer: SPANSION [SPANSION]

Mode Register Update and Deep Sleep Timings
Notes:
1. Minimum cycle time for writing register is equal to speed grade of product.
August 30, 2004 pSRAM_Type01_12_A1
Chip deselect to ZZ# low
ZZ# low to WE# low
Write register cycle time
Chip enable to end of write
Address valid to end of write
Write recovery time
Address setup time
Write pulse width
Deep Sleep Pulse Width
Deep Sleep Recovery
LB#, UB#
ZZ#
A4
CE#
WE#
CE#
ZZ#
Item
Figure 31. Deep Sleep Mode - Entry/Exit Timings (for 32M and 16M)
Figure 30. Deep Sleep Mode - Entry/Exit Timings (for 64M)
t
t
AS
ZZWE
A d v a n c e
t
CDZZ
t
t
WC
AW
t
BW
t
WP
I n f o r m a t i o n
Symbol
t
t
t
ZZMIN
ZZWE
CDZZ
t
t
t
t
t
t
WC
CW
AW
WR
WR
t
pSRAM Type 1
AS
R
t
t
ZZMIN
t
ZZMIN
WR
70/85
70/85
70/85
200
Min
10
40
10
5
0
0
Max
500
t
R
t
R
Unit
ns
ns
ns
ns
ns
ns
ns
ns
µs
µs
Note
1
1
1
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