XC68HC705JJ7 Motorola, XC68HC705JJ7 Datasheet - Page 68

• Manufacturer Part Number: XC68HC705JJ7
• Description: MICROCONTROLLER
• Manufacturer: Motorola

Resets
5.5 Internal Resets
5.5.1 Power-On Reset (POR)
5.5.2 Computer Operating Properly (COP) Reset
Advance Information
68
The four internally generated resets are:
Only the COP watchdog timer reset, low-voltage reset, and illegal
address detector will also assert the pulldown device on the RESET pin
for the duration of the reset function or for three to four internal bus
cycles, whichever is longer.
The internal POR is generated on power-up to allow the clock oscillator
to stabilize. The POR is strictly for power turn-on conditions and is not
able to detect a drop in the power supply voltage (brown-out); that
function can be performed by the LVR. Depending on the DELAY bit in
the mask option register (MOR), there is an oscillator stabilization delay
of 16 or 4064 internal bus cycles after the LPO becomes active.
The POR will generate the RST signal which will reset the CPU. If any
other reset function is active at the end of the 16- or 4064-cycle delay,
the RST signal will remain in the reset condition until the other reset
condition(s) end.
POR will not activate the pulldown device on the RESET pin. V
drop below V
V
A timeout of the COP watchdog generates a COP reset. The COP
watchdog is part of a software error detection system and must be
cleared periodically to start a new timeout period. To clear the COP
watchdog and prevent a COP reset, write a logic 0 to the COPC bit of the
COPR register at location $1FF0. The COPC bit, shown in
Figure
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Initial power-on reset (POR) function
COP watchdog timer reset
Low-voltage reset (LVR)
Illegal address detector
5-2, is a write-only bit.
POR
for the internal POR circuit to detect the next rise of
Resets
MC68HC705JJ7 • MC68HC705JP7 — REV 4
MOTOROLA
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must