XC68HC705JJ7 Motorola, XC68HC705JJ7 Datasheet - Page 155

• Manufacturer Part Number: XC68HC705JJ7
• Description: MICROCONTROLLER
• Manufacturer: Motorola

10.4 Core Timer Counter Register
MC68HC705JJ7 • MC68HC705JP7 — REV 4
MOTOROLA
TOF = 1/(f
MHz
488
4.2
Interrupt Period
(Microseconds)
Timer Overflow
@ f
OSC
1024
MHz
2.0
OSC
(MHz)
Table 10-1. Core Timer Interrupt Rates and COP Timeout Selection
2048
MHz
1.0
2
11
)
RT1 RT0
0
0
1
1
Address:
A 15-stage ripple counter driven by a divide-by-eight prescaler is the
basis of the core timer. The value of the first eight stages is readable at
any time from the read-only timer counter register as shown in
Figure
Power-on clears the entire counter chain and begins clocking the
counter. After the startup delay (16 or 4064 internal bus cycles
depending on the DELAY bit in the mask option register (MOR)), the
power-on reset circuit is released, clearing the counter again and
allowing the MCU to come out of reset.
Reset:
Read:
Write:
0
1
0
1
divided
= f
10-3.
Rate
$0009
Figure 10-3. Core Timer Counter Register (CTCR)
RTI
by:
2
2
2
2
Bit 7
Bit 7
OSC
15
16
17
18
0
MHz
7.80
15.6
31.2
62.4
= Unimplemented
4.2
Interrupt Period
(Milliseconds)
@ f
6
6
0
Real-Time
Core Timer
OSC
(RTI)
MHz
16.4
32.8
65.5
131
2.0
(MHz)
5
5
0
MHz
32.8
65.5
131
262
1.0
4
4
0
54.6
Min
109
218
437
4.2 MHz
Max
62.4
COP = 7-to-8 RTI Periods
125
250
499
3
3
0
COP Timeout Period
(Milliseconds)
@ f
Core Timer Counter Register
Min
115
229
459
918
2.0 MHz
OSC
2
2
0
(MHz)
1049
Max
131
262
524
Advance Information
1
1
0
1835
Min
229
459
918
1.0 MHz
Core Timer
Bit 0
Bit 0
1049
2097
Max
262
524
0
155