XC68HC705JJ7 Motorola, XC68HC705JJ7 Datasheet - Page 166

• Manufacturer Part Number: XC68HC705JJ7
• Description: MICROCONTROLLER
• Manufacturer: Motorola

Programmable Timer
Advance Information
166
TCAP
PB3
AN3
RESET
SUBSYSTEM
ANALOG
FROM
CONTROL
CPF2
FLAG
ICEN
BIT
BIT
Figure 11-6. Timer Input Capture Block Diagram
SELECT
Address:
Address:
READ
ICRH
INPUT
MUX
The input capture registers are made up of two 8-bit read-only registers
(ICRH and ICRL) as shown in
detector contains a Schmitt trigger to improve noise immunity. The edge
that triggers the counter transfer is defined by the input edge bit (IEDG)
in the TCR. Reset does not affect the contents of the input capture
registers.
Reset:
Reset:
Read:
Read:
Write:
Write:
Figure 11-7. Input Capture Registers (ICRH and ICRL)
& DETECT
$0014
$0015
SELECT
LOGIC
EDGE
Bit 15
$0012
Bit 7
Bit 7
Bit 7
TIMER CONTROL REG.
Programmable Timer
= Unimplemented
LATCH
14
6
6
6
ICRH ($0014)
INPUT CAPTURE (ICF)
16-BIT COUNTER
13
5
5
5
Figure
ICRL ($0015)
Unaffected by reset
Unaffected by reset
MC68HC705JJ7 • MC68HC705JP7 — REV 4
12
TIMER STATUS REG.
4
4
4
11-7. The input capture edge
11
3
3
3
$0013
4
10
2
2
2
INTERNAL
INTERNAL
DATA
DATA
BUS
BUS
INTERNAL
(OSC
READ
INTERRUPT
ICRL
CLOCK
REQUEST
TIMER
1
9
1
1
2)
MOTOROLA
Bit 0
Bit 8
Bit 0
Bit 0