XC68HC705JJ7 Motorola, XC68HC705JJ7 Datasheet - Page 55

• Manufacturer Part Number: XC68HC705JJ7
• Description: MICROCONTROLLER
• Manufacturer: Motorola

4.5 Software Interrupt
4.6 External Interrupts
4.6.1 IRQ/V
MC68HC705JJ7 • MC68HC705JP7 — REV 4
MOTOROLA
PP
NOTE:
Pin
The software interrupt (SWI) instruction causes a non-maskable
interrupt.
These sources can generate external interrupts:
Setting the I bit in the condition code register or clearing the IRQE bit in
the interrupt status and control register disables these external
interrupts.
An interrupt signal on the IRQ/V
request. To help clean up slow edges, the input from the IRQ/V
processed by a Schmitt trigger gate. When the CPU completes its
current instruction, it tests the IRQ latch. If the IRQ latch is set, the CPU
then tests the I bit in the condition code register and the IRQE bit in the
IRQ status and control register (ISCR). If the I bit is clear and the IRQE
bit is set, then the CPU begins the interrupt sequence. The CPU clears
the IRQ latch while it fetches the interrupt vector, so that another external
interrupt request can be latched during the interrupt service routine. As
soon as the I bit is cleared during the return from interrupt, the CPU can
recognize the new interrupt request.
external interrupts.
If the IRQ/V
The IRQ/V
and low level-triggered. External interrupt sensitivity is programmed with
the LEVEL bit in the mask option register (MOR).
•
•
IRQ/V
PA3–PA0 pins
PP
PP
PP
pin can be negative edge-triggered only or negative edge-
pin is not in use, it should be connected to the V
pin
Interrupts
PP
pin latches an external interrupt
Figure 4-3
shows the logic for
Advance Information
Software Interrupt
PP
DD
Interrupts
pin is
pin.
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