XC68HC705JJ7 Motorola, XC68HC705JJ7 Datasheet - Page 59

• Manufacturer Part Number: XC68HC705JJ7
• Description: MICROCONTROLLER
• Manufacturer: Motorola

MC68HC705JJ7 • MC68HC705JP7 — REV 4
MOTOROLA
IRQF — External Interrupt Request Flag
like filter capacitors and a crystal or ceramic resonator and consumes
more power. The selection and enable conditions for these two
oscillators are shown in
Therefore, the lowest power is consumed when OM1 is cleared. The
state with both OM1 and OM2 set is provided so that the EPO can be
started and allowed to stabilize while the LPO still clocks the MCU.
The reset state is for OM1 to be cleared and OM2 to be set, which
selects the LPO and disables the EPO.
The IRQ flag is a clearable, read-only bit that is set when an external
interrupt request is pending. Writing to the IRQF bit has no effect.
Reset clears the IRQF bit.
The following conditions set the IRQ flag:
The following conditions clear the IRQ flag:
OM2
1 = Interrupt request pending
0 = No interrupt request pending
• An external interrupt signal on the IRQ/V
• An external interrupt signal on pin PA0, PA1, PA2, or PA3
• When the CPU fetches the interrupt vector
• When a logic 1 is written to the IRQR bit
0
0
1
1
when the PA0–PA3 pins are enabled by the PIRQ bit in the MOR
to serve as external interrupt sources.
OM1
0
1
0
1
Oscillator
Selected
External
by CPU
Internal
Internal
Internal
Interrupts
Table 4-2. Oscillator Selection
Table
Low-Power
Oscillator
Disabled
Enabled
Enabled
Enabled
Internal
(LPO)
4-2.
Oscillator
External
Disabled
Disabled
Enabled
Enabled
(EPO)
Pin
PP
pin
Advance Information
External Interrupts
Consumption
Normal
Normal
Lowest
Lowest
Power
Interrupts
59