XC68HC705JJ7 Motorola, XC68HC705JJ7 Datasheet - Page 164

• Manufacturer Part Number: XC68HC705JJ7
• Description: MICROCONTROLLER
• Manufacturer: Motorola

Programmable Timer
Advance Information
164
NOTE:
flag bit and timer interrupts. The alternate counter registers include a
transparent buffer latch on the LSB of the 16-bit timer counter.
The alternate counter registers (ACRH and ACRL) shown in
Figure 11-5
low bytes of the 16-bit free-running counter. Writing to the alternate
counter registers has no effect. Reset of the device presets the timer
counter to $FFFC.
The ACRL latch is a transparent read of the LSB until a read of the
ACRH takes place. A read of the ACRH latches the LSB into the ACRL
location until the ACRL is again read. The latched value remains fixed
even if multiple reads of the ACRH take place before the next read of the
ACRL. Therefore, when reading the MSB of the timer at ACRH, the LSB
of the timer at ACRL must also be read to complete the read sequence.
During power-on reset (POR), the counter is initialized to $FFFC and
begins counting after the oscillator startup delay. Because the counter is
16 bits and preceded by a fixed prescaler, the value in the counter
repeats every 262,144 internal bus clock cycles (524,288 oscillator
cycles).
Reading the ACRH and ACRL in any order or any number of times does
not have any effect on the 16-bit free-running counter or the TOF flag bit.
To prevent interrupts from occurring between readings of the ACRH and
ACRL, set the I bit in the condition code register (CCR) before reading
ACRH and clear the I bit after reading ACRL.
RESET
READ
ACRH
$FFFC
Figure 11-4. Alternate Counter Block Diagram
READ
are read-only locations which contain the current high and
Programmable Timer
ACRH ($001A)
LATCH
16-BIT COUNTER
MC68HC705JJ7 • MC68HC705JP7 — REV 4
ACRL ($001B)
TMR LSB
4
MOTOROLA
INTERNAL
INTERNAL
(OSC
READ
ACRL
CLOCK
DATA
BUS
2)