txc-03456 TranSwitch Corporation, txc-03456 Datasheet - Page 77

• Manufacturer Part Number: txc-03456
• Description: Device Level Mapper
• Manufacturer: TranSwitch Corporation

Address
1B
1C
Bit
0
7
6
5
2
1
0
LOADEN
RESETC
RESETD
RESETS
Symbol
PARDO
BSAISE
AC1EN
Load Enable: Used for desynchronizer operation. The internal pointer
leak counter shall be preset with the 15-bit leak rate value using the fol-
lowing steps:
1. Write the value to the seven upper bits (with 7 being the MSB),
2. Write the 8-bit value into the lower register (1A).
3. Write a 1 to this bit, or write the seven upper bits in this register, along
This bit is set to 1 after a device reset.
Reset Counters: A 1 causes the performance counters to reset. When
the reset is completed, this bit is self clearing and this bit position
becomes a 0.
Reset Mapper: A 1 resets the Mapper. The Mapper will remain reset
until the processor writes a 0 into this location.
Reset Desynchronizer: A 1 resets the two FIFOs in the desynchronizer
to mid-range values.
Parity Data Byte Only: A common bit for both the drop and add buses,
and valid for all timing modes. A 1 enables parity to be calculated for
data bytes only. A 0 enables parity to be calculated for the add bus out-
put signals, and drop bus input signals.
Add Bus C1 Pulse Enable: A 1 enables the C1 pulse to be transmitted
as a separate signal instead of in the AC1J1 signal in the external and
drop timing modes. A 0 enables the AC1J1 signal to carry both the C1
and J1 signals. In the add bus timing mode, the C1 signal can be applied
on the AC1 pin instead of in the C1J1 signal independent of the state of
this bit.
Bit Stuffing AIS Enable: A 1 causes an internal bit stuffing implementa-
tion to be used for the transmit and receive 140 Mbit/s line AIS genera-
tion instead of using the external AIS clock. This bit is set to 0 upon
power-up (selecting the external AIS clock). When the bit stuffing AIS
feature is selected, the receive performance monitor circuit and AIS
detection circuits are disabled when receive AIS is generated automati-
cally by the L4M. Please note that the loss of the drop bus clock will dis-
able the generation of receive AIS based on bit stuffing.
and a 0 to this bit.
with a 1 to this bit. The internal counter will preset with the 15-bit
value on the 0 to 1 transition.
DATA SHEET
- 77 -
Description
Ed. 1A, January 2000
TXC-03456
TXC-03456-MB
L4M