txc-03456 TranSwitch Corporation, txc-03456 Datasheet - Page 49

• Manufacturer Part Number: txc-03456
• Description: Device Level Mapper
• Manufacturer: TranSwitch Corporation

Test Generator and Analyzer
The L4M is equipped with a transmit test generator and receive analyzer. A simplified block diagram of the test
generator and analyzer is shown in Figure 23 below. The transmit clock (TXC) must be present in order for the
2
The test generator is enabled by writing a 1 to control bit TGEN (bit 2 in 14H). The byte or nibble transmit input
is disabled and the test sequence is enabled. The test generator can be also be enabled when the L4M is in
line loopback. The 2
writing a 1 to control bit ANAEN (bit 1 in 14H). The test analyzer monitors the incoming test sequence for lock,
using consecutive 1000-bit blocks (not a sliding window). An out of lock alarm (ANOOL) is detected when 30
bits in a 1000-bit sequence are detected in error. Recovery occurs when the first 24 bits in the test sequence
match. Errors are counted in a 16-bit performance counter (locations 44 and 45H). The counter is inhibited
when out of lock or when the analyzer is disabled.
23
-1 test generator to function. The test generator sequence is specified in ITU-T recommendation O.151.
FIFO
Xmit
23
-1 test analyzer samples the receive data for operation. The test analyzer is enabled by
Data
Clock
Test Generator
Desync
Circuit
Enable
Figure 23. Test Generator, Analyzer and Loopback
Test Analyzer
Enable
Data
Clock
Data
Pattern
Clock
Test
Clock
Data
Generator
Analyzer
Transmit
Receive
Output
Block
Block
Input
Test
Test
DATA SHEET
- 49 -
NIB Lead
NIB Lead
Data
Clock
Loopback
Enable
Rec Data (Byte/Nibble)
Rec Clock
Xmit Data (Byte/Nibble)
Xmit Clock
Ed. 1A, January 2000
TXC-03456
TXC-03456-MB
L4M